A PID SRF‐PLL based algorithm for positive‐sequence synchrophasor measurements

Abstract

Summary Most of the proposed algorithms for synchrophasor estimation are based on the Discrete Fourier Transform (DFT). However, this technique has well‐known limitations, such as the leakage effect. Alternatively, this paper presents a positive‐sequence synchrophasor measurement algorithm based on a Synchronous Reference Frame Phase‐Locked Loop (SRF‐PLL). The algorithm is modular and consists of four stages. The first one is the abc‐dq transform that, with the aid of the second stage, a Finite Impulse Response (FIR) provides the positive‐sequence of the grid voltages. The filter also helps to improve the signal‐to‐noise ratio. This filter class was chosen due to its characteristic of linear phase and constant group delay to avoid unwanted phase distortions at the measurements. The third stage is an SRF‐PLL based on a PID controller that estimates the amplitude and phase of the grid voltage's positive‐sequence component and the grid frequency. By assessing the dynamic condition tests, it was observed that the PLL could not comply with all the IEEE standard requirements. Therefore, a fourth stage was included to calculate the frequency, and Rate of Change of Frequency (ROCOF) based on the estimated positive‐sequence phase. Experimental results obtained with a test platform shown that the proposed algorithm complies with all IEEE C37.118.1‐2011 and C37.118.1a‐2014 standard requirements.

Implementation of Phasor Measurement Unit Based on Phase-Locked Loop Techniques: A Comprehensive Review

“…The reporting rate used in this work is 25 FPS, and according to experimental results provided in [35], the proposed algorithm complies with the IEEE standard [4][5][6][7] for both classes P and M. Adding filters against input signal noise and harmonics presents positive results even in the out-of-band interference tests.…”

“…In addition, the implementation of the algorithm presents a low computational burden, making it capable of being developed on a general-purpose microcontroller with DSP features. The experimental results showed that the proposed PLL-based PMU algorithm for the synchrophasor estimation complies with all the IEEE standard requirements [4,7] for both PMU classes P and M, while in conjunction with the low computational cost, makes it attractive for implementation of low-cost PMUs in order to be used in distribution networks [35], although it provides a low reporting rate.…”

“…The authors in [35] implemented an SRF-PLL-based algorithm to estimate the positive sequence of the synchrophasor, employing the symmetrical components' theorem of Fortescue introduced in [36]. A microcontroller unit (MCU) is used to examine the compatibility of the proposed algorithm with the IEEE standard [4][5][6][7] for classes P and M. In (15), the positive-, negative-and zero-sequence components are presented, where…”

“…In Figure 4, the block dia gram of the proposed SRF-PLL-based algorithm for positive-sequence synchrophasor es timation is presented where the hat denotes the corresponding estimated value. The reporting rate used in this work is 25 FPS, and according to experimental results provided in [35], the proposed algorithm complies with the IEEE standard [4][5][6][7] for both…”