A Secure Reconfigurable Crypto IC With Countermeasures Against SPA, DPA, and EMA

Abstract

IndexTerms-Side-channel attack, Reconfigurable architecture, Cryptographic Coprocessor, correlation based differential analysis (CPA), electromagnetic analysis (EMA).Abstract-A secure reconfigurable cryptographic co-processor (SRCP) supporting multiple algorithms of AES, DES, RC6 and IDEA is proposed using its own reconfigurable feature to resist Side-channel attack (SCA). It is integrated into a system-on chip and fabricated in 0.18 μm CMOS process with 1.8 V supply voltage and 100 MHz max frequency. Several kinds of specific countermeasures are proposed to hide leakage information by utilizing idle reconfigurable processing elements (PEs) to do dummy operations. Its advantages lie in its little impact on area and frequency as well as high flexibility after silicon that countermeasures can also be reconfigured. Furthermore, different protections including several kinds of global countermeasures and encryption flow related countermeasures can be stacked, thus the security level can be tuned by trading for some performance or power consumption. Experimental SCA attack results show that it resists SPA and DPA without revealing the subkey. For correlation based EMA of DES configuration, it increases 36× measure to disclosure when applied with partial countermeasures compared to unprotected DES. As to AES configuration with full countermeasures, it resists EMA with no sign to reveal the right subkey for up to 1.2 million electromagnetic traces.

Side-Channel Power Resistance for Encryption Algorithms Using Implementation Diversity

“…Swankoski et al [22] propose the use of a parallel architecture to achieve temporal isolation of the key. Shan et al [23] propose countermeasures to hide leakage information by utilizing idle reconfigurable processing elements to do dummy operations. Levi et al [24] propose a delay assignment algorithm that assigns buffer delays to combinational logic to implement data-dependent delays, as a means of mitigating single-bit and multi-bit CPA attacks.…”

A novel differential fault analysis using two‐byte fault model on AES Key schedule

“…Due to the strict mathematical structure of advance encryption standards (AES) [1], AES-based cryptosystem has been proved to immune against most conventional attacks. However, with the development of physical attacks such as side-channel attack (SCA) [2,3] and fault attacks (FA) [4], it has shown vulnerabilities for hardware implementation of AES [5][6][7][8][9].…”

High Secured Low Power Multiplexer-LUT Based AES S-Box Implementation

“…However, in practical applications, the circuit charges may not be perfectly balanced, hence the power dissipation profile correlates to the charging and discharging of the circuit activities can easily leak out some pertinent information. In another study, the reconfigurable IC is implemented [6] to countermeasure against the CPA attack. The countermeasure technique utilized idle reconfigurable processing elements to generate dummy operations as to reduce the correlation.…”