A Self-Calibrated Fractional-N PLL for WiFi 6 / 802.11ax in 28nm FDSOI CMOS

Vlachogiannakis, Gerasimos; Basetas, Charis; Τσιριμώκου, Γεωργία; Vassou, Chrysoula; Vastarouchas, Konstantinos; Georgiadou, Aidonia; Sotiriou, Ioulia; Korfiati, Timothea; Sgourenas, S.

doi:10.1109/esscirc.2019.8902919

Cited by 10 publications

(4 citation statements)

References 6 publications

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“…It is calculated as the percentage of the total mean bit rate concerning the maximum cell capacity. 5. Throughput: in a communication network is the total bit rate of successful message delivery over a communication channel.…”

Section: B Performance Parametersmentioning

confidence: 99%

Performance Evaluation of 5G/WiFi-6 Coexistence

Zreikat

2020

International Journal of Circuits, Systems and Signal Processing

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The fifth-generation mobile communication network (5G) is the promising technology nowadays to provide not only a higher speed compared to 4G but also a revolution of services to cover different industrial sectors such as health, production, energy, and many. WiFi-6 is a new wireless local area network (WLAN) technology that is suitable to work in an office, home, and dense areas. As a new technology, 5G has some limitations concerning coverage and capacity. To overcome these limitations, one possible solution is to use the free unlicensed spectrum available in Wi-Fi technology, therefore, a complement solution of 5G/WiFi-6 coexistence is proposed to make both technologies complement each other in providing a better quality of service for the end-user concerning a higher speed, low latency, and higher capacity. According to OFDM modulation, the proposed model divides the cell into two virtual zones, the inner zone represents WiFi-6 technology surrounded by 5G technology. All resources will be shared between the two technologies taken into consideration that more bandwidth should be given to the most inner zone with high intensity of traffic. The call admission control algorithm will be based on a minimum bit rate to be given to each zone that should be satisfied to admit the call. The model is solved using MOSEL-2 simulation language, to study different performance parameters such as BER, utilization, blocking probability, latency, throughput, and aggregate average bit rate in both zones. The simulation results show that coexistence causes some degradation in 5G performance, however, a positive effect on the overall cell performance is achieved by balancing the load all over the whole cell.

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Section: B Performance Parametersmentioning

confidence: 99%

Performance Evaluation of 5G/WiFi-6 Coexistence

Zreikat

2020

International Journal of Circuits, Systems and Signal Processing

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“…2. To achieve this, the true single-phase clocking (TSPC) PFD are desirable due to its simple logic and short delay path [54] . In addition, the source degeneration technique can also be used to reduce the current noises of current sources in the CP [55,56] , and the ratio between the CP bias current and the CP output cannot be too small.…”

Section: In-band Phase Noise Reduction Techniquesmentioning

confidence: 99%

CMOS analog and mixed-signal phase-locked loops: An overview

Zhang¹

2020

J. Semicond.

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CMOS analog and mixed-signal phase-locked loops (PLL) are widely used in varies of the system-on-chips (SoC) as the clock generator or frequency synthesizer. This paper presents an overview of the AMS-PLL, including: 1) a brief introduction of the basics of the charge-pump based PLL, which is the most widely used AMS-PLL architecture due to its simplicity and robustness; 2) a summary of the design issues of the basic CPPLL architecture; 3) a systematic introduction of the techniques for the performance enhancement of the CPPLL; 4) a brief overview of ultra-low-jitter AMS-PLL architectures which can achieve lower jitter (< 100 fs) with lower power consumption compared with the CPPLL, including the injection-locked PLL (ILPLL), sub-sampling (SSPLL) and sampling PLL (SPLL); 5) a discussion about the consideration of the AMS-PLL architecture selection, which could help designers meet their performance requirements.

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“…In most cases, this is difficult to achieve with simple circuit configurations. While usually the voltage variations can be easily managed by supplying the oscillators with voltage regulators [4], the temperature and process variations require more complicated designs or additional control setups and calibrations [5,6]. Thus, regarding the temperature influence on the VCO operation, the performance of current steering oscillators could be compensated by using temperature-dependent current sources, e.g., proportional to absolute temperature (PTAT) or complementary to absolute temperature (CTAT), for temperature variation [6].…”

Section: Introductionmentioning

confidence: 99%

A Linear Multi-Band Voltage-Controlled Oscillator with Process Compensation for SerDes Applications

Bertsias,

Tsimpos,

Souliotis

2024

Electronics

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A new voltage-controlled oscillator (VCO) topology for serializer–deserializer (SerDes) applications is proposed in this paper. The topology is suitable for SATA, PCI Express, and USB 3 protocols. The VCO is based on two-ring oscillator cores and operates in several frequency bands, as required by the corresponding protocol specifications, with a constant VCO gain and improved linear control over the frequency tuning. Additionally, it is supported by an automatic digital compensation mechanism for process variations. The VCO has been designed to cover the several speeds of the SATA and PCI Express protocols, with optimized performance in all of them, including the current consumption, the phase noise, and the frequency tuning in each case. Designed in a CMOS 22 nm technology node with a 0.8 V supply voltage, it can achieve, at 3 GHz frequency, a phase noise better than −90 dBc/Hz at 1 MHz offset and an average power consumption equal to 3.84 mW. Extended digital control can set optimized configurations for phase noise, current consumption, and VCO gain vs. process variations. Extensive post-layout simulation results verify the superior performance.

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A Self-Calibrated Fractional-N PLL for WiFi 6 / 802.11ax in 28nm FDSOI CMOS

Cited by 10 publications

References 6 publications

Performance Evaluation of 5G/WiFi-6 Coexistence

Performance Evaluation of 5G/WiFi-6 Coexistence

CMOS analog and mixed-signal phase-locked loops: An overview

A Linear Multi-Band Voltage-Controlled Oscillator with Process Compensation for SerDes Applications

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