A self-checking ALU design with efficient codes

Gorshe, Steve; Bose, B.

doi:10.1109/vtest.1996.510851

Cited by 29 publications

(6 citation statements)

References 3 publications

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“…-Berger check prediction [Gorshe and Bose 1996;Lo et al 1992]; -Bose-Lin check prediction [Gorshe and Bose 1996;Mitra and McCluskey 2000]; -parity (or modulo-2) checking [Sellers et al 1968;Hsiao and Sellers 1963]; and -residue (or modulo-3) checking [Sellers et al 1968;Langdon and Tang 1970].…”

Section: Scau Ed/ec Analysismentioning

confidence: 99%

“…However, since [Gorshe and Bose 1996] report that in a 16-bit adder with 2 Bose-Lin code bits (capable of detecting single arithmetic errors, and double unidirectional errors) the area cost is significantly lower than that of utilizing BCP, BLCP (with a limited number of code bits) ought to be cheaper than full hardware duplication. Implementation and analysis are required to provide an answer, since it cannot be found in the literature.…”

Section: Berger and Bose-lin Check Predictionmentioning

confidence: 99%

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Towards scalable arithmetic units with graceful degradation

Riemens

Gaydadjiev

Zeeuw

et al. 2014

ACM Trans. Embed. Comput. Syst.

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This article presents a new family of scalable arithmetic units (ScAUs) targeting resource-constrained, embedded devices. We, first, study the performance, power, area and scalability properties of general adders. Next, suitable error-detection schemes for low-power embedded systems are discussed. As a result, our ScAUs are enhanced with a suitable error-detection scheme, resulting in a Parity-Checked ScAU (PCScAU) design. The PCScAU strikes a flexible trade-off between space and time redundancy, offering dependability similar to high-end techniques for the area and power cost of low-end approaches. An alternative design, the Precision-Scalable Arithmetic Unit (PScAU) maintains throughput with degraded precision in case of hardware failures. The PScAU is targeting dependable applications where latency rather than numerical accuracy is more important. The PScAU's downscaled mode is also interesting for runtime thermal management due to its advantageous power consumption. We implemented and synthesized the PCScAU, PScAU and a few important reference designs (double-, triple-and quadruple-modular-redundancy adders with/without input gating) in 90-nm UMC technology. Overall, the PC-ScAU ranks first in 9 out of 10 power-delay-area (PDA)-product variants. It exhibits 16% area savings and 12% performance speedup for 7% increase in total power consumption, compared to the cheapest form of conventional hardware replication with the same fault coverage. The PDA product of the PCScAU is, thus, reduced by 21%. It is interesting that, while total power slightly increases, the PCScAU static power in fact decreases by 14%. Therefore, for newer technology nodes where the static power component is significant, the PCScAU can also achieve-next to performance and area -significant power improvements.

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Section: Scau Ed/ec Analysismentioning

confidence: 99%

Section: Berger and Bose-lin Check Predictionmentioning

confidence: 99%

Towards scalable arithmetic units with graceful degradation

Riemens

Gaydadjiev

Zeeuw

et al. 2014

ACM Trans. Embed. Comput. Syst.

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“…Inputs I and outputs O for circuits are extended to code words, which are checked to detect errors. Codes for arithmetic circuits include, e.g., parity (the number of ones in I modulo 2), the Berger code (the number of zeros in I), as reported in (Lo et al, 1993), Bose-Lin Codes, described in (Gorshe and Bose, 1996), or the residue code reported in (Sparmann and Reddy, 1994). Figure 10 shows a parity checked CSA with a final CRA.…”

Section: Self-checking Addersmentioning

confidence: 99%

New Self-Checking Booth Multipliers

Hunger¹,

Marienfeld²

2008

International Journal of Applied Mathematics and Computer Science

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This work presents the first self-checking Booth-3 multiplier and a new self-checking Booth-2 multiplier using parity prediction. We propose a method which combines error-detection of Booth-3 (or Booth-2) decoder cells and parity prediction. Additionally, code disjointness is ensured by reusing logic for partial product generation. Parity prediction is applied to a carry-save-adder with the standard sign-bit extension. In this adder almost all cells have odd fanouts and faults are detected by the parity. Only one adder cell has an even fanout in the case of Booth-3 multiplication. Especially, for even-number Booth-2 multipliers parity prediction becomes efficient. Since that prediction slightly differs from previous work which describes CSA-folded adders, formulas to predict the parity are developed here. The proposed multipliers are compared experimentally with existing solutions. Only 102% of the area of Booth-2 without error detection is needed for the self-checking Booth-3 multiplier.

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“…Функции g i подбираются таким образом, чтобы сформированный на выходах блока логиче-ского дополнения вектор <h 1 h 2 … h n > принадлежал вектору заранее выбранного помехо-устойчивого кода [4][5][6][7][8][9][10]. Таким образом, данное соответствие определяется на этапе проектирования системы функционального контроля и контролируется в процессе ее экс-плуатации с использованием полностью самопроверяемого тестера TSC (Totally Self-Checking Checker), на выходах которого формируется парафазный контрольный сигнал [11].…”

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Organization of functional control systems with totally self-checking structure based on paraphase signals compression modules

Sapozhnikov¹,

Ефанов²

2017

Izv. vysš. učebn. zaved., Priborostr.

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Предложена стандартная структура системы функционального контроля на ос-нове метода логического дополнения. Установлены правила вычисления функ-ций логического дополнения, позволяющие обеспечивать полную самопрове-ряемость структуры системы функционального контроля. Сформулированы ус-ловия, предъявляемые к контролируемому логическому устройству, выполне-ние которых гарантированно позволяет синтезировать полностью самопрове-ряемую систему функционального контроля.Ключевые слова: система функционального контроля, логическое дополнение, полностью самопроверяемая структура, модуль сжатия парафазных сигналов

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A self-checking ALU design with efficient codes

Cited by 29 publications

References 3 publications

Towards scalable arithmetic units with graceful degradation

Towards scalable arithmetic units with graceful degradation

New Self-Checking Booth Multipliers

Organization of functional control systems with totally self-checking structure based on paraphase signals compression modules

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