A Self-Reconfigurable Hardware Architecture for Mesh Arrays Using Single/Double Vertical Track Switches

Fukushi, Masaru; Horiguchi, Susumu

doi:10.1109/tim.2003.822717

Cited by 23 publications

(7 citation statements)

References 21 publications

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“…Using the same assumptions as in [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34], [35], [36], [37], [38], [39], [40], [41], [42], [43], all switches and interconnects in an array are assumed to be fault-free. This assumption is justified since the switches and links use much less hardware resources when compared to the PEs and are thus less vulnerable to faults.…”

Section: Simulation Resultsmentioning

confidence: 99%

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Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms

Jiang

et al. 2015

IEEE Trans. Comput.

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With the increased density of three-dimensional (3D) processor arrays, faults can potentially occur quite often due to power overheating during massively parallel computing. In order to achieve fault-tolerance under such a scenario, an effective way is to find an as large as possible logical fault-free subarray of m 0 Â n 0 Â h 0 from a faulty array of m Â n Â h (m 0 m; n 0 n; h 0 h), such that an original application can still work on the m 0 Â n 0 Â h 0 subarray. This paper investigates the problem of constructing maximum fault-free subarrays with minimum interconnection length from 3D arrays with faults. First, we prove that constructing maximum logical array (MLA) is NP-complete. We propose a linear-time algorithm which is capable of producing an MLA for the problem with the constraint of selected indexes. Second, we prove that minimizing the interconnection length (inter-length) of the MLA is NP-hard. We propose an efficient heuristic which significantly reduces the inter-length by revising each logical plane of the MLA. This leads to the reduction of communication cost, capacitance and dynamic power dissipation. In addition, we propose a lower bound for the inter-length of the MLA to evaluate the proposed algorithms. Simulation results show that, the size of logical array can be improved up to 62.6 percent in average, and the inter-length redundancy can be reduced by 22.7 percent in average, compared to the state-of-the-art, for all cases considered.Index Terms-3D processor array, fault tolerance, maximum logical array, interconnection length, NP-complete problem, algorithm Ç G. Jiang is with the

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Section: Simulation Resultsmentioning

confidence: 99%

“…Switches will not be used in bypass scheme. For the layout of PEs, switches, links, I/O port selector, bypass controller and some practical issues related to the reconfigurable arrays, please refer to the reference [33]. In a similar manner, the x-bypass and y-bypass schemes can be obtained.…”

Section: D Architecture and Notationsmentioning

confidence: 99%

Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms

Jiang

et al. 2015

IEEE Trans. Comput.

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“… utilized genetic approaches to evolve rerouting strategies for constructing logical rows/columns in designing the MLA. Methods that employ different tracks and switches to increase harvest on the reconfigurable processor arrays are discussed in . Utilizing the heuristic approach and dynamic programming, Jigang et al .…”

Section: Introductionmentioning

confidence: 99%

“…Fukushi et al [14,15] utilized genetic approaches to evolve rerouting strategies for constructing logical rows/columns in designing the MLA. Methods that employ different tracks and switches to increase harvest on the reconfigurable processor arrays are discussed in [16][17][18][19][20][21]. Utilizing the heuristic approach and dynamic programming, Jigang et al [22] proposed two reconfiguration algorithms to construct a high-performance subarray by reducing the number of long interconnects.…”

Section: Introductionmentioning

confidence: 99%

Efficient abstraction algorithms for accelerating reconfiguration of VLSI arrays

Qian

Bai

Zhou

et al. 2017

IEEJ Transactions Elec Engng

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Employment of fault‐tolerant techniques is necessary for the operability and reliability of very large scale integration (VLSI) arrays. Moreover, fault tolerance must be obtained at high speed on real‐time embedded systems. In this paper, a novel abstract model, based on the abstraction technique, is proposed to accelerate the reconfiguration of degradable VLSI arrays with low fault density. Given an m × n physical array with faults, the proposed technique extracts some physical rows including faulty elements to construct an abstraction array, ignoring the physical rows without faults, such that the size of original physical array can be significantly reduced to speed up the reconfiguration of VLSI array. In addition, we conclusively demonstrate the preservation of properties between the abstract array and the physical array to guarantee that the proposed technique is correct. Experimental results show that for a 128 × 128 physical array with 0.1% faults, a 15 × 128 abstract array can be constructed and the compression is more than 88.20%. This abstraction technique is bound into a reconfiguration algorithm cited in this paper. Simulation results show that the running time can be improved by more than 66.79% for a 128 × 128 physical array with 0.1% faults. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

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“…In contrast to the [5][6][7][8][9][10], in which some spare PEs are used to replace faulty PEs, the degradation approach uses as much fault-free PEs as possible to derive a fault-free array. Kuo [11] classified the reconfiguration problems of degradable processor arrays into three different classes, namely 1)…”

Section: : Introductionmentioning

confidence: 99%

An Improved Reconfiguration Method for Degradable Processor Arrays Using Genetic Algorithm

Fukushima

Fukushi

Horiguchi

2006

2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

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This paper addresses the NP-complete problem of reconfiguring two-dimensional degradable processor arrays under the row and column rerouting constraint. One promising approach to this problem is to treat the reconfiguration problem as a combinatorial optimization problem of finding the set of rerouting rules for all rows/columns and employ a genetic algorithm (GA) to obtain an optimal solution [1]. However, major drawback of this method is poor utilization of processing elements (PEs) in the reconfiguration process. In this paper, we improve the previous method [1] for efficient reconfiguration. The key idea is to treat the reconfiguration problem as an optimization problem of determining routing directions for all faulty PEs. A new rerouting scheme is also proposed to reroute logical rows/columns efficiently. Experimental study shows that the proposed method produces good results in terms of the percentage of harvest and degradation.

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A Self-Reconfigurable Hardware Architecture for Mesh Arrays Using Single/Double Vertical Track Switches

Cited by 23 publications

References 21 publications

Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms

Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms

Efficient abstraction algorithms for accelerating reconfiguration of VLSI arrays

An Improved Reconfiguration Method for Degradable Processor Arrays Using Genetic Algorithm

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