A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology

Abstract

This paper describes an on-chip instrument for the estimation of absolute and period random jitter of clock signals in the GHz range with a sub-picosecond resolution. A selfreferenced technique is used to remove the need of a very clean external reference clock. The instrument has been designed in STMicroelectronics 28 nm FDSOI technology. By exploiting the fine delay control which can be achieved with this technology, simulation results haven shown a resolution down to 100 fs for GHz clock signals with a simple calibration procedure. The instrument meets the requirement of a small footprint while using a standard digital test interface to transfer data. It can be configured in different ways to suit the resolution and frequency of operation requirements. I.

A sub-picosecond resolution jitter instrument for GHz frequencies based on a sub-sampling TDA

“…5 which utilizes the modified TDA, and reports the results obtained for jitter measurement of signals up to 5 GHz. This instrument is built on the basis of our previous jitter estimation instrument in [10], where operation at such high frequency is not possible due to limitations in the classical TDA. A clock signal injected with a known value of RMS jitter is fed as input Signal Under Test (SUT) to the test instrument.…”

“…It must be noticed that the implementation only considers sampling one side of the SUT random jitter PDF that is considered symmetrical. The described operation is similar to the one described in [10] that has been proven to be robust against process variations.…”

“…The signal Select Rise Fall that finally controls the latching of TDA inputs for amplification by the 4-stage TDA is sent half a clock period in advance and hence setup and hold time requirements of the input latches will be respected. Mismatch between the two control latches will shift the output jitter histogram, but this is corrected during a simple calibration step of the instrument similarly as in [10].…”

“…Recently, an instrument with automatic calibration has been demonstrated in a 28 nm CMOS process but with picosecond resolution with signals up to 1 GHz [9]. Authors presented in [10] a novel self-referenced jitter instrument combining the use of a Vernier delay line with a TDA, demonstrating sub-picosecond resolution for GHz frequencies.…”

Special Session: On-chip jitter BIST with sub-picosecond resolution at GHz frequencies

“…This paper has presented an implementation of an onchip jitter BIST in 28 nm FDSOI with simulation results that demonstrate the feasibility of a sub-picosecond resolution for jitter estimation for clocks up to 1 GHz. The FDSOI technology provides advantages due to tunability and low noise to reach a high resolution with simple calibration as described in [6]. A highly tunable delay element along with a TDA supports a sub-picosecond resolution of clock jitter measurement for frequencies in the GHz range.…”