A Semi-Parallel Successive-Cancellation Decoder for Polar Codes

Abstract

Polar codes are a recently discovered family of capacity-achieving codes that are seen as a major breakthrough in coding theory. Motivated by the recent rapid progress in the theory of polar codes, we propose a semi-parallel architecture for the implementation of successive cancellation decoding. We take advantage of the recursive structure of polar codes to make efficient use of processing resources. The derived architecture has a very low processing complexity while the memory complexity remains similar to that of previous architectures. This drastic reduction in processing complexity allows very large polar code decoders to be implemented in hardware. An polar code successive cancellation decoder is implemented in an FPGA. We also report synthesis results for ASIC.

Folded successive cancelation decoding of polar codes

“…Research has developed along two lines: (i) reducing SC complexity implementation (ii) improving the error performance with higher complexity decoders. Along the first line, efficient SC decoder implementations have been studied in [3], [4], [5], [6], based on specific methods to optimize the SC decoder in hardware. In [5], a specific scheduling for butterfly-based SC decoder was presented enabling resource sharing to reduce complexity.…”

“…In [5], a specific scheduling for butterfly-based SC decoder was presented enabling resource sharing to reduce complexity. A semi-parallel decoder was proposed in [6] as a simple architecture for resource sharing with a small increase in latency. Along the second line, to improve error performance, higher complexity decoders have been investigated such as list decoder in [7], belief propagation (BP) in [9], [8] and the sphere decoding based maximum likelihood (ML) decoders in [10], [11].…”

Fast software polar decoders

“…As shown in [3], this can be carried out without the use of multiplications or divisions by expressing probabilities as loglikelihood-ratios (LLRs), denoted λ, and applying the minsum (MS) approximation. The decision rule forû i becomeŝ…”

“…For example, despite using a smaller number of quantization bits, the semi-parallel polar decoder of [3] offers an inferior throughput for the (2048, 1707) and (32768, 29462) codes, achieving only 69.2 Mbps and 27.6 Mbps respectively, whereas the SIMD-int8 decoder reaches 198.7 Mbps and 226.9 Mbps. The decoder is also faster than the hardware polar decoders of [5,8].…”

“…Many hardware implementations of the successive-cancellation (SC) algorithm were able to exploit the regular structure of polar codes to reduce implementation complexity [3][4][5].…”