A Server Cache Size Aware Cache Replacement Algorithm for Block Level Network Storage

Nagasako, Yusuke; Yamaguchi, Saneyasu

doi:10.1109/isads.2011.80

Cited by 9 publications

(2 citation statements)

References 6 publications

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“…It maintains a timestamp or a reference bit for each cache block and updates it whenever a block is accessed. When a replacement is needed, the block with the oldest timestamp or the least recently accessed block is chosen for eviction [10], [11]. • First-In, First-Out (FIFO) Replacement: In the FIFO replacement policy, the cache block that was first loaded into the cache is replaced.…”

Section: Literature Reviewsmentioning

confidence: 99%

Improving Cache Hits On Replacment Blocks Using Weighted LRU-LFU Combinations

Wijaya

2023

IJRITCC

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Block replacement refers to the process of selecting a block of data or a cache line to be evicted or replaced when a new block needs to be brought into a cache or a memory hierarchy. In computer systems, block replacement policies are used in caching mechanisms, such as in CPU caches or disk caches, to determine which blocks are evicted when the cache is full and new data needs to be fetched. The combination of LRU (Least Recently Used) and LFU (Least Frequently Used) in a weighted manner is known as the "LFU2" algorithm. LFU2 is an enhanced caching algorithm that aims to leverage the benefits of both LRU and LFU by considering both recency and frequency of item access. In LFU2, each item in the cache is associated with two counters: the usage counter and the recency counter. The usage counter tracks the frequency of item access, while the recency counter tracks the recency of item access. These counters are used to calculate a combined weight for each item in the cache. Based on the experimental results, the LRU-LFU combination method succeeded in increasing cache hits from 94.8% on LFU and 95.5% on LFU to 96.6%.

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Section: Literature Reviewsmentioning

confidence: 99%

Improving Cache Hits On Replacment Blocks Using Weighted LRU-LFU Combinations

Wijaya

2023

IJRITCC

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“…If so, the processor will read from or write to the cache instead of the much slower main memory, which makes the processes within the system much faster. Nearly all current desktop and server CPUs have at least three autonomous caches [2]: an instruction cache to speed up executable instruction fetch, a data cache to speed up data fetch and store, lastly a translation lookaside buffer (TLB) used to speed up virtual-to-physical address translation for both executable instructions and data. A single TLB can be provided for access to both instructions and data, or a separate Instruction TLB (ITLB) and data TLB (DTLB) can be provided.…”

Section: Overview Of Cache Memorymentioning

confidence: 99%

An Overview of Cache Memory in Memory Management

Abayomi¹,

Olukayode²,

Olakunle³

2020

ACIS

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Cache memory are used in small, medium and high speed Central Processing Unit (CPU) to hold provisionally those content of the main memory which are currently in use. Preferably, Caches ought to have low miss rates, short access times, and power efficient at the same time. The design objectives are frequently gainsaying in practice. Nowadays, security concern about caches information outflow is based on the proficient attack of the information in the memory and the design for security in the cache memory are even more controlled and typically leads to significant cache performance. Fault tolerance is an additional advantage of the cache architecture which can be guaranteed in the memory to overcome the processor speed gap in the memory, the routine gap between processors and main memory continues to broaden, increasingly aggressive implementations of cache memories are needed to bridge the gap. In this paper, the objective is to make cache memory unsurprising as seen by the processor, so it can be used in hard real time system to achieve this we consider some of the issues that are involved in the implementation of highly optimized cache memories and survey the techniques that can be used to help achieve the increasingly stringent design targets.

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