1977
DOI: 10.1109/tns.1977.4328725
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A Shared Random Access Memory Resource for Multiprocessor Real-Time Systems

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Cited by 13 publications
(1 citation statement)
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“…This arrangement is shown in Fig There are two additional devices connected to the processor UNIBUS, the first of which is the multiport memory. This is a device whereby several processors may communicate to common data arrays contained in a 30 bit address space distinct from the local processor address space (Dimmler and Hardy, .1977). Each processor reads or writes in the memory through an access port.…”
Section: Methodsmentioning
confidence: 99%
“…This arrangement is shown in Fig There are two additional devices connected to the processor UNIBUS, the first of which is the multiport memory. This is a device whereby several processors may communicate to common data arrays contained in a 30 bit address space distinct from the local processor address space (Dimmler and Hardy, .1977). Each processor reads or writes in the memory through an access port.…”
Section: Methodsmentioning
confidence: 99%