A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing

Abstract

Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption and other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC and its design techniques. The IC has been fabricated in 0.18µm CMOS. The coprocessor, which is used for embedded cryptographic and biometric processing, consists of four components: an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint-matching oracle, a template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first, 'secure', coprocessor is implemented using a logic style called Wave Dynamic Digital Logic (WDDL) and a layout technique called differential routing. The second, 'insecure', coprocessor is implemented using regular standard cells and regular routing techniques. Measurement-based experimental results show that a differential power analysis (DPA) attack on the insecure coprocessor requires only 8,000 acquisitions to disclose the entire 128b secret key. The same attack on the secure coprocessor still does not disclose the entire secret key at 1,500,000 acquisitions. This improvement in DPA resistance of at least 2 orders of magnitude makes the attack de facto infeasible. The required number of measurements is larger than the lifetime of the secret key in most practical systems.

Overcoming Glitches and Dissipation Timing Skews in Design of DPA-Resistant Cryptographic Hardware

“…As the transistor size and wiring width continuously shrink, it becomes more difficult to apply such techniques. Besides, current results show that these approaches needs area at least 3 times larger than the standard CMOS implementation of an unprotected AES design [14].…”

“…The attack, called as Differential Power Analysis (DPA), has been considered as the most dangerous attack to the security of cryptographic embedded systems [9]. A recent report stated that the key of an unprotected AES coprocessor can be found in less than three minutes [14].…”

“…The first approach attempts to make the power consumption constant regardless of what intermediate result being produced. A straightforward method is to use the dual rail logic [7,10,12,14], that represents a data bit by a pair of complementary wires and takes the same number of transitions regardless of what data value it transfers.…”

“…The requirement is hard to meet in standard semi-custom design environment. Balanced cell design [7] and differential routing technique [14] are proposed to treat the problem. As the transistor size and wiring width continuously shrink, it becomes more difficult to apply such techniques.…”

Securing Sensor Nodes Against Side Channel Attacks

“…Previous work on side channel attacks has studied information leakage from monitors [29], keyboards [6,10,39], consumer mobile devices (such as PDAs, pagers) [18], IC chips [37], smart cards [32], etc. However, no previous work has focussed on preventing side channel attacks on sensor nodes.…”