A sigma-delta modulator with residual offset suppression

Abstract

This Letter presents a low-residual-offset second-order sigma-delta modulator. By inserting a chopper working at low frequency to the mirrored integrator at the first stage of the modulator, the original residual offset is transferred to a high frequency, which can be removed by the filter. Besides, by applying the second-order fractal sequence as the timing of the new added chopper, the residual offset accumulation problem due to the integration at the second stage can be avoided. To evaluate the effect of residual offset suppression conveniently, a programmable timing is integrated to the design to control the state of the added chopper. The presented modulator is fabricated in a 0.18 um CMOS technology, the core area of which is 0.38 mm 2 . Based on the measurement results, the DC offset of the sigma-delta modulator with the proposed method is reduced by 85.6 μV. The modulator realizes 64.8 dB dynamic range with 1 MHz sampling rate, which consumes 0.96 mW from a 3.3 V supply.

A Machine Learning Approach for the Forecasting of Computing Resource Requirements in Integrated Circuit Simulation

“…A circuit simulation task consists of the circuit, simulation options, and simulator. In this experiment, the collected circuits were taken from several sources, including standard textbooks [17,18] and papers in the literature [19][20][21][22][23][24], which are designed using standard foundry analog libraries and commercial CMOS technology. The simulation options are set by circuit design experts; Spectre X, APS, and UltraSim are selected as simulators.…”