A simple and high-performance 130 nm SOI eDRAM technology using floating-body pass-gate transistor in trench-capacitor cell for system-on-a-chip (SoC) applications

Kumar, M.; Steigerwalt, Michael; Walsh, B.; Doney, T.L.; Wildrick, D.; Bard, K.; Dobuzinsky, D.; McFarland, P.A.; Schiller, C.; Messenger, Brian; Rathmill, S.E.; Gasasira, Arthur; Parries, P.; Iyer, Subu; Chaloux, S.; Ho, H.

doi:10.1109/iedm.2003.1269312

Cited by 3 publications

(2 citation statements)

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“…For the 64-ls retention, this limit will be approximately 1.8 nm to 2.0 nm for conventional oxide gate dielectrics. These same device considerations can be applied to adapt the silicon-on-insulator devices used in the highest-performance logic technologies for use as an array device [25].…”

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confidence: 99%

Embedded DRAM: Technology platform for the Blue Gene/L chip

et al. 2005

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The Blue Genet/L chip is a technological tour de force that embodies the system-on-a-chip concept in its entirety. This paper outlines the salient features of this 130-nm complementary metal oxide semiconductor (CMOS) technology, including the IBM unique embedded dynamic random access memory (DRAM) technology. Crucial to the execution of Blue Gene/L is the simultaneous instantiation of multiple PowerPCt cores, highperformance static random access memory (SRAM), DRAM, and several other logic design blocks on a single-platform technology. The IBM embedded DRAM platform allows this seamless integration without compromising performance, reliability, or yield. We discuss the process architecture, the key parameters of the logic components used in the processor cores and other logic design blocks, the SRAM features used in the L2 cache, and the embedded DRAM that forms the L3 cache. We also discuss the evolution of embedded DRAM technology into a higherperformance space in the 90-nm and 65-nm nodes and the potential for dynamic memory to improve overall memory subsystem performance.

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Section: Figure 16mentioning

confidence: 99%

Embedded DRAM: Technology platform for the Blue Gene/L chip

et al. 2005

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“…There has been increasing interest of embedded dynamic random access memory ͑DRAM͒ for system-on-chip ͑SoC͒ application. [1][2][3] The advantages of embedding DRAM to logic circuits are increased bandwidth, reduced power consumption, and small die size. However, there are critical problems such as degraded refresh time in DRAM cells and low yield caused by increased processing steps when one embeds standard DRAM cells to logic processes.…”

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confidence: 99%

Characterization of Three-Dimensional Capacitor Prepared by Oxide Recess in Shallow Trench Isolation

Suh¹,

Cho²,

Jeong³

et al. 2005

J. Electrochem. Soc.

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In this paper, we present a new process flow to increase cell capacitance in planar dynamic random access memory cells designed for system-on-chip applications. Silicon dioxide of shallow trench isolation ͑STI͒ under capacitor electrodes is recessed to increase cell capacitance. It appears that the cell capacitance is increased to 25% when the STI recess is 0.15 m. The recession slightly decreases junction leakage current due to annealing of defects and also relief of STI stress. These combined effects increase refresh time about 50% in 1 Mb memory array. The distribution of breakdown voltage in capacitor oxide shows similar behavior compared with samples without STI recessed. Also, the lifetime of the capacitor oxide evaluated from the Weibull method exceeds 2000 years.There has been increasing interest of embedded dynamic random access memory ͑DRAM͒ for system-on-chip ͑SoC͒ application. 1-3 The advantages of embedding DRAM to logic circuits are increased bandwidth, reduced power consumption, and small die size. However, there are critical problems such as degraded refresh time in DRAM cells and low yield caused by increased processing steps when one embeds standard DRAM cells to logic processes. This is caused by incompatibility between DRAM and logic processes. While the DRAM process focuses on the reduction of cell size with sacrifice of device performance, the logic process mainly focuses on enhancing device performance by using processes such as dual-gate transistors, salicide, and multilevel metals. Unfortunately, these steps in the logic process degrade the refresh time of DRAM cells and also reduce total yield due to increased process steps. 4,5 Recently, planar DRAM cells are investigated to solve these problems. Planar DRAM cells consist of a pass transistor and a metal-oxide-semiconductor ͑MOS͒ capacitor. Although its cell size is normally 6-8 times larger than stack or trench type DRAM cells, it uses a standard logic process and thus enables use of a standard logic library and intellectual properties. 6 The weak point of planar DRAM cells compared with stack cells is a reduced cell capacitance because it uses only two dimensions. Although one can increase cell capacitance by increased cell area, packing density is reduced due to increased die size. The other way could be to use thinner gate oxide or high dielectric constant material such as silicon nitride or tantalum oxide. However, it becomes difficult to implement this in a logic compatible process.In this paper, we present a new process flow to increase cell capacitance in planar DRAM cells by partial recess of shallow trench isolation ͑STI͒. It appears that the cell capacitance is increased up to 25% when the recessed depth is 0.15 m. The measured reliability of the capacitor oxide has no difference compared with the sample without STI recession. These combinations enhance the refresh time of DRAM cells. Figure 1 shows a vertical structure of the DRAM cell used in this study. It has a p-MOS access transistor and a planar capacitor. The main char...

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Common-source-line array

Zhao

Yang

Zhang

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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Traditional array organization of bipolar nonvolatile memories such as STT-MRAM and memristor utilizes two bitlines for cell manipulations. With technology scaling, such bitline pair will soon become the bottleneck for further density improvement. In this article we propose a novel common-source-line array architecture, which uses a shared source-line along the row, leaving only one bitline per column. We elaborate the array design to ensure reliability, and demonstrate its effectiveness on STT-MRAM and memristor memory arrays. Our study results show that with comparable latency and energy, the proposed common-source-line array can save 34% and 33% area for Memristor-RAM and STT-MRAM respectively, compared with corresponding dual-bitline arrays.

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A simple and high-performance 130 nm SOI eDRAM technology using floating-body pass-gate transistor in trench-capacitor cell for system-on-a-chip (SoC) applications

Cited by 3 publications

References 5 publications

Embedded DRAM: Technology platform for the Blue Gene/L chip

Embedded DRAM: Technology platform for the Blue Gene/L chip

Characterization of Three-Dimensional Capacitor Prepared by Oxide Recess in Shallow Trench Isolation

Common-source-line array

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