A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip

Stensgaard, Mikkel Bystrup; Bjerregaard, Tobias; Sparsø, Jens; Pedersen, J.H.

doi:10.1109/dsd.2006.17

Cited by 7 publications

(5 citation statements)

References 7 publications

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“…This leads to conclusions which support asynchronous implementation of NoC routers and links. Section V reviews the implementation of a couple of asynchronous NoCs designed at DTU [7], [8], [9], [10], [11], [12], [13], and finally section VI concludes the paper.…”

Section: Imentioning

confidence: 99%

“…Despite the potential bottleneck where the roots of the two trees are connected the NoC supports more than 10 data transfers in one clock period, without any need for generating this higher frequency clock. More details are available in [13]. Should more bandwidth be needed, a different NoC topology offering a higher bisection bandwidth may easily be implemented using the same merge and switch components.…”

Section: B the Audio Dsp Nocmentioning

confidence: 99%

“…The design is significantly more complex than the audio DSP NoC, and the details are beyond the scope of this paper. The interested reader is referred to [7], [8], [9], [10], [11], [12], [13]. A prototype router for a 2D-mesh topology (c.f., figure 1) has been designed and implemented using standard cells in a 0.130 micron technology.…”

Section: The Mango Nocmentioning

confidence: 99%

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Asynchronous design of networks-on-chip

Sparsø

2007

Norchip 2007

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Section: Imentioning

confidence: 99%

Section: B the Audio Dsp Nocmentioning

confidence: 99%

See 1 more Smart Citation

Asynchronous design of networks-on-chip

Sparsø

2007

Norchip 2007

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“…Examples at industrial level are presented in [10], [9], [17], [5]. In [9] authors examine the use of GALS techniques to address on-chip communication between different synchronous modules on a bus.…”

Section: Related Workmentioning

confidence: 99%

Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs

Ludovici¹,

Strano²,

Gaydadjiev³

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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There is today little doubt on the fact that a high-performance and cost-effective Network-on-Chip can only be designed in 45nm and beyond under a relaxed synchronization assumption. In this direction, this paper focuses on a GALS system where the NoC and its end-nodes have independent clocks (unrelated in frequency and phase) and are synchronized via dual-clock FIFOs at network interfaces. Within the network, we assume mesochronous synchronization implemented with hierarchical clock tree distribution. This paper contributes two essential components of any practical design automation support for network instantiation in the target system. On one hand, it introduces a switch design which greatly reduces the overhead for mesochronous synchronization and can be adapted to meet different layout constraints. On the other hand, the paper illustrates a design space exploration framework of mesochronous links that can direct the selection of synchronization options on a portby-port basis for all the switches in the NoC, based on timing and layout constraints. A final case study illustrates how a cost-effective GALS NoC can be assembled, placed and routed by exploiting the flexibility of the architecture and the outcomes of the exploration framework, thus proving the viability and effectiveness of the design platform.

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“…For these application-specific NoCs, the workloads, traffic patterns, and constraints are known apriori [6]. Stensgaard et al [7], for example, present a case study for a DSP audio chip to prove the effectiveness of an NoC in comparison to the initial design with a crossbar. The application aims at a unidirectional data transfer rate in the range of kilobits per second (kbit/s) whereas this paper describes the implementation of a packet processing system for gigabit Ethernet (GbE).…”

Section: Introductionmentioning

confidence: 99%

Mapping a Pipelined Data Path onto a Network-on-Chip

Kubisch

Cornelius

Hecht

et al. 2007

2007 International Symposium on Industrial Embedded Systems

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During the last years, Networks-on-Chip (NoCs) have become a true alternative for the design of complex integrated Systems-on-Chip (SoC). Much effort has been spent for research on functionalities, mechanisms, and Quality-of-Service (QoS) features in NoCs. Hence, a broad and multi-faceted design space exists but leaves open, which mechanisms and design paradigms actually tip the scales for the chosen application domain. In this paper, we discuss the level of QoS needed in a specific NoC for a packet processing application. This is done in the light of preliminary investigations for the redesign of an existing packet processing system because that system's current architecture exhibits drawbacks regarding performance and further scalability. Therefore, we considered to take advantage of an NoC communication architecture. A simple NoC was developed, which knowingly omits sophisticated QoS mechanisms. Relying on the lessons, which have learned from the history and development of the Internet, we argue that a simple and plain NoC suffices for applications as the one discussed.

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A Simple Clockless Network-on-Chip for a Commercial Audio DSP Chip

Abstract: We design a very small, packet-switched, clockless Network-on-Chip (NoC)

Cited by 7 publications

References 7 publications

Asynchronous design of networks-on-chip

Asynchronous design of networks-on-chip

Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs

Mapping a Pipelined Data Path onto a Network-on-Chip

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