A simple recursive digital sinusoidal oscillator with uniform frequency spacing

Al-Ibrahim, M.M.

doi:10.1109/iscas.2001.921164

Cited by 12 publications

(15 citation statements)

References 7 publications

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“…In particular, the derivations of some reduced structures for digital sine-cosine generators that produce the two sinusoidal sequences that are exactly 90 degrees out of phase with each other is first discussed. These circuits have many applications in many signal processing systems such as the computation of the Discrete Fourier Transform (DFT) [8,9]. They can also form the backbone of certain orthogonal modulation systems utilized in recent optical and mobile communications.…”

Section: Realizations Of Single-multiplier Digital Sine-cosine Generatormentioning

confidence: 99%

“…A digital sinusoidal oscillator with low and uniform frequency spacing was presented by M. AI-Ibrahim and A. Al-Khateeb [7], but it requires three 14-bit multipliers for its hardware implementation. M. Al-Ibrahim presented then a simple recursive digital sinusoidal oscillator with uniform frequency spacing [8]. Nevertheless, such oscillator structure also required a single 14-bit multiplier for its hardware implementation.…”

Section: Introductionmentioning

confidence: 99%

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Performance Analysis of Single-Multiplier Digital Sine-Cosine Generators

Abdul–Jabbar¹,

Qaqos²

2012

(AREJ)

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In this paper, second order structures satisfying single-multiplier digital sine-cosine generators are derived analytically, resulting in four different realizations. Some important characteristics of these generator structures, like total harmonic distortion percentage (THD%), frequency error (and frequency resolution are defined and examined as performance measures. The four generator realizations are simulated using Matlab7.0 program. The simulation results show that better performance (THD% and are very low or negligible) can be obtained for these realizations by using 32 bits to represent the single-multiplier coefficient and other the outputs of arithmetic operations. The rounding-off method is applied as a quantization process after multiplication process. A comparison is made between one of the best-derived structures and other two recent structures implemented in previous researches. The comparison results indicate that better performance measures can be achieved from the proposed realization for the single-multiplier digital sine-cosine generator.

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Section: Realizations Of Single-multiplier Digital Sine-cosine Generatormentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Single-Multiplier Digital Sine-Cosine Generators

Abdul–Jabbar¹,

Qaqos²

2012

(AREJ)

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“…DDFS_s can be categorized as recursive [4,5], and non-recursive types [6][7][8][9][10][11][12][13][14][15][16][17][18][19][20]. The recursive DDFS_s are notorious for their error-propagation problem, due to their error feedback nature, although the algorithm [4] has the advantage of only needing two multiplication and two addition operations to generate one sine and one cosine values.…”

Section: Introductionmentioning

confidence: 99%

“…Also, they are hard to pipeline, because only when the current function value is obtained, can the next function value be calculated. A solution to reduce errorpropagation is presented in [5]. However, it needs four multiplication and four addition operations per output data sample.…”

Section: Introductionmentioning

confidence: 99%

“…Besides, its output SFDR performance is poorer than those existing designs with the same internal data path word length. In addition, the recursive DDFS_s [4,5] are only suitable for the application of fixed frequency control word q and zero initial angle value. To make q flexible and adjustable, they need a very large table to store a wide range of cosq value.…”

Section: Introductionmentioning

confidence: 99%

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Direct Digital Frequency Synthesis Based on a Two-Level Table-Lookup Scheme

Chen

Chih

Chou

2006

J VLSI Sign Process Syst Sign Image Video Technol

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In this work, a new direct digital frequency synthesizer (DDFS) is proposed, which is based on a new two-level table-lookup (TLTL) scheme combined with Taylor_s expansion. This method only needs a lookup-table size of total n Â 2 n=4þ1 þ n=4 À 2 ð ÞÂ2 n=4 bits, one n þ 1 ð ÞÂ3n=4 À bit multiplier, one nÂ3n/4-bit multiplier and two additional smaller multipliers, to generate both sine and cosine values (where n is the output precision). Compared with several notable DDFS_s, the new design has a smaller lookup-table size and higher SFDR (Spurious Free Dynamic Range) for high-precision output cases, at comparable multiplier and adder complexities. The DDFS is verified by FPGA and EDA tools using Synopsys Design Analyzer and UMC 0.25 mm cell library, assuming 16-bit output precision. The designed 16-bit DDFS has a small gate count of 2,797, and a high SFDR of 110 dBc.

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A new hardware-efficient digital sinusoidal oscillator with low- and uniform-frequency spacing

Al-Ibrahim

2003

Electrical Engineering (Archiv fur Elektrotechnik)

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A simple recursive digital sinusoidal oscillator with uniform frequency spacing

Cited by 12 publications

References 7 publications

Performance Analysis of Single-Multiplier Digital Sine-Cosine Generators

Performance Analysis of Single-Multiplier Digital Sine-Cosine Generators

Direct Digital Frequency Synthesis Based on a Two-Level Table-Lookup Scheme

A new hardware-efficient digital sinusoidal oscillator with low- and uniform-frequency spacing

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