A Simplified 8 × 8 Transformation and Quantization Real-Time Ip-Block for Mpeg-4 H.264/AVC Applications: A New Design Flow Approach

Abstract

Current multimedia design processes suffer from the excessively large time spent on testing new IP-blocks with references based on large video encoders specifications (usually several thousands lines of code). The appropriate testing of a single IP-block may require the conversion of the overall encoder from software to hardware, which is difficult to complete in the short time required by the competition-driven reduced time-to-market demanded for the adoption of a new video coding standard. This paper presents a new design flow to accelerate the conformance testing of an IP-block using the H.264/AVC software reference model. An example block of the simplified 8 × 8 transformation and quantization, which is adopted in FRExt, is provided as a case study demonstrating the effectiveness of the approach.

A high-throughput ASIC processor for 8×8 transform coding in H.264/AVC

“…(4) are avoided if Eqs. (17) and (18) are applied in the forward quantization. However, the parameter lev must be implemented instead of lev_off defined in Eq.…”

“…For any other QP/6 value, only 18-QP/6 bits would be necessary to represent M, as can be easily deduced from the definition of qbits in expression (5) used in Eq. (17). Therefore, the left shifting operation (MS = M5QP/6) requires 18 À QP/ 6+QP/6 =18 bits independently of QP.…”

“…In contrast, the architecture presented in [14] unifies all transforms supported by FRExt with an efficient quantization/dequantization scheme to reduce the latency without increasing the hardware cost. Other 8 Â 8 transform and quantization designs implemented on FPGAs have been proposed such as the configurable forward and inverse architecture in [15], the simplified forward 8Â 8 transform and quantization architecture, which is capable of processing 64 data/cycle in [16] and its corresponding IP-block in [17], the reduced hardware architecture in [18], which processes pixel by pixel and where the quantization is done without a real multiplier, and the integrated solution in FPGA to perform all transforms and the quantization, which supports luma and chroma for intra-or inter-configurations in [19]. It is worth mentioning other implementations such as the one based on a VLIW+SIMD architecture [20], the unified video CODEC for standards JPEG, MPEG-1/2/4, H.264 and VC-1 [21] or the hardware-sharing designs for the standards H.264 and AVS (developed in China) [22].…”

Fast Calculation of 8 × 8 Integer DCT in the Software Implementation of H.264/AVC

“…Hardware solutions such as Refs. [3][4][5][6][7][8][9] have been proposed to accelerate the computational intensive parts of H.264 encoder.…”

“…4,5 Consequently, the hardware implementation of the integer 8 Â 8 DCT transform attracted attentions and a number of solutions have been published for hardware implementation of 8 Â 8 transform of the H.264/AVC standard. [6][7][8][9] Even though, many real-time systems use the software implementation of 8 Â 8 integer DCT and high computation load of 8 Â 8 integer DCT is not desirable in these applications, there is not any well known proposed algorithm to reduce the computational complexity of reference software in implementation of 8 Â 8 integer DCT. Since the H.264/AVC high pro¯le codec applies both of 8 Â 8 and four 4 Â 4 integer DCT to each 8 Â 8 block, we decided to propose a method to reuse the coe±cients generated by 4 Â 4 integer DCT of 8 Â 8 block in the computation of 8 Â 8 integer DCT.…”