A Simulation Study of SiGe Shell Channel CFET for Sub-2-nm Technology Nodes

Shi, Xinlong; Liu, Tao; Wang, Ying; Chen, Rui; Xu, Min; Wang, Liming; Hu, Huiyong

doi:10.1109/ted.2023.3238393

Cited by 3 publications

(1 citation statement)

References 34 publications

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“…However, semiconductor device scaling degrades the performance due to short-channel effects and band-to-band tunneling. To overcome these issues, vertical nanosheet FETs are promising candidates for next-generation logic, memory applications, artificial synapses, and neurons. − While this work focuses on optimizing the device design through simulation for synapse applications, it is possible to develop a practical process architecture based on previous studies. − The engineered vertically stacked nanosheet can be fabricated through monolithic integration of a 3D field-effect transistor. − …”

Section: Introductionmentioning

confidence: 99%

Engineered Vertically Stacked NSFET Charge-Trapping Synapse for Neuromorphic Applications

Raza Ansari,

Navlakha,

El-Atab

2023

ACS Appl. Electron. Mater.

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Section: Introductionmentioning

confidence: 99%

Engineered Vertically Stacked NSFET Charge-Trapping Synapse for Neuromorphic Applications

Raza Ansari,

Navlakha,

El-Atab

2023

ACS Appl. Electron. Mater.

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Electrical Characteristic and Power Fluctuations of GAA Si NS CFETs by Simultaneously Considering Six Process Variation Factors

Kola,

2023

IEEE Open J. Nanotechnol.

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Characteristic variability induced by process variation effect (PVE) is one of technological challenges in semiconductor industry. In this work, we computationally study electrical characteristic and power fluctuations induced by six factors of PVE of the gate-all-around (GAA) silicon (Si) nanosheet (NS) complementary field-effect-transistors (CFETs) which are formed by vertically stacking n-FET on top of p-FET. Among the six factors, NS thickness (TNS), NS width (WNS), and gate length (LG) are identified as crucial factors contributing to large variations in device characteristics. The p-FET exhibits substantial off-state current fluctuation (about 151%) due to the bottom parasitic channel leakages. Compared with the magnitudes of dynamic and short circuit powers, the static power is marginal, but it possesses the largest fluctuation (up to 148%). If we assume that each factor of PVE has the same probability distribution as the others and all are mutually independent, the statistical sum of their power fluctuations will exhibit more than 50% overestimations, compared with the results when all factors are considered simultaneously.

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Silicon-Germanium Ultrashort-Gate Transistor Performances by Electrical-Thermal Simulations

Yamakiri,

Sugiura,

Yamamura

et al. 2024

IEEE Trans. Nanotechnology

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A Simulation Study of SiGe Shell Channel CFET for Sub-2-nm Technology Nodes

Cited by 3 publications

References 34 publications

Engineered Vertically Stacked NSFET Charge-Trapping Synapse for Neuromorphic Applications

Engineered Vertically Stacked NSFET Charge-Trapping Synapse for Neuromorphic Applications

Electrical Characteristic and Power Fluctuations of GAA Si NS CFETs by Simultaneously Considering Six Process Variation Factors

Silicon-Germanium Ultrashort-Gate Transistor Performances by Electrical-Thermal Simulations

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