A Simulation Tool for Space Applications: RadiSPICE

Muhikanci, Omer Yusuf; Ozanoglu, Kemal; Afacan, Engín; Yelten, Mustafa Berke; Dündar, Günhan

doi:10.1109/smacd55068.2022.9816181

Cited by 2 publications

(1 citation statement)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…This change may then propagate to a sequential logic element such as a flip-flop creating a bit flip that changes the stored value which is known as a SEU. The propagation of SETs and the occurrence of SEUs can be simulated at the circuit level to better understand the probability that a given radiation particle creates an error [9]. In FPGAs, SEUs on memories are dominant and therefore, developing fault tolerant FPGA designs for harsh environments is a primary concern.…”

Section: Introductionmentioning

confidence: 99%

Systematic Reliability Evaluation of FPGA Implemented CNN Accelerators

Gao

Yao

et al. 2023

IEEE Trans. Device Mater. Relib.

View full text Add to dashboard Cite

Convolutional neural networks (CNN) have become essential for many scientific and industrial applications, such as image classification and pattern detection. Among the devices that can implement neural networks, SRAM based FPGAs are a popular option due to their excellent parallel computing capability and good flexibility. However, SRAM-FPGAs are susceptible to radiation effects, which limits its application on safety critical applications. In this paper, the reliability of an accelerator based on the advanced Instruction-Set Architecture is evaluated based on hardware fault injection experiments. Each main module of the accelerator is evaluated separately, and the impact of parallelism and model features on the accelerator reliability is also examined. The experimental results reveal some important conclusions in terms of general hardware reliability and also of the particular model reliability. First, over 99% of SEUs on the computation modules will cause accuracy loss, and the reliability improves for higher parallelism. Second, a large portion of SEUs on the data mover and the instruction scheduler will cause system corruptions due to abnormal interactions with the ARM or other modules. Third, nonlinear activation and pooling layers are effective in reducing the effect of SEUs on computation modules, so models that use these layers tend to be more robust. The results provide a deep understanding of the impact of errors on CNNs implemented on ISA based FPGA accelerators (e.g., the Xilinx DPU).

show abstract

Section: Introductionmentioning

confidence: 99%