A Simulator for Large-Scale Parallel Computer Architectures

Abstract

Efficient design of hardware and software for large-scale parallel execution requires detailed understanding of the interactions between the application, computer, and network. The authors have developed a macro-scale simulator (SST/macro) that permits the coarse-grained study of distributed-memory applications. In the presented work, applications using the Message Passing Interface (MPI) are simulated; however, the simulator is designed to allow inclusion of other programming models. The simulator is driven from either a trace file or a skeleton application. Trace files can be either a standard format (Open Trace Format) or a more detailed custom format (DUMPI). The simulator architecture is modular, allowing it to easily be extended with additional network models, trace file formats, and more detailed processor models. This paper describes the design of the simulator, provides performance results, and presents studies showing how application performance is affected by machine characteristics.

Network-accelerated non-contiguous memory transfers

“…To analyze the effects of integrating sPIN in next-generation networks, we extend the Cray Slingshot Simulator, which models a 200 Gib/s NIC (see Fig. 1) in Sandia Structural Simulation Toolkit (SST) [34], adding packet processing capabilities by implementing sPIN. We configure the network simulator to send 2KiB of payload data.…”

Fast and Faithful Performance Prediction of MPI Applications: the HPL Case Study

“…Here, the application is executed (emulated) on top of a simulator that is responsible to determine when each process is run. This approach allows researchers to study directly the behavior of MPI applications but only a few recent simulators such as SST Macro [12], SimGrid/SMPI [1] and the closed-source xSim [13] support it. To the best of our knowledge, only SST Macro and SimGrid/SMPI are mature enough to faithfully emulate HPL.…”

OpenSoC Fabric

“…In addition, many multiprocessor simulators include an on-chip network, or support integration with a dedicated on-chip network simulator [8,20,30].…”