A sine/cosine direct digital frequency synthesizer using an angle rotation algorithm

Abstract

A quadrature direct digital frequency synthesizer @DFS) produces 16b sine and cosine outputs with a spurious-free dynamic range greater than lOOdBc and a tuningresolution of 0.0015 Hz at a sample rate of 1OOMHz. The prototype IC contains 58,000 transistors in a core area of 12mm2 in 1.0pm CMOS and dissipates 1.4W at 1OOMHz.Instead of table lookup, an angle-rotation algorithm implemented as a multiplierless feedforward datapath is used that allows easy pipelining and Limits the accumulation of roundoff errors 111. The modular architecture permits outputs of arbitrary precision by cascading enough angle rotation stages in the datapath.The computation of sine and cos6 can be viewed as the computation of the X-axis and the Y-axis coordinates of a phasor, initially coincident with the X-axis, rotated by an angle 8 on the unit circle. Cordic iteratively computes angle rotations and has been used for frequency synthesis [21. Cordic approximates a rotation by a sequence of N subrotations through angles Oi 80 that e = a1 + a, 8, + ... + % ON. If Bi = tan-' 2.' and CL, ~[ -l , 11, the datapath is multiplierless. The a,s are determined iteratively and require knowledge of the sign of the difference between two angles at each iteration. The throughput of the cordic datapath canbe improved by using redundant arithmetic (e.g., carry-save) eliminating the carry-propagation delay. However, detection of the sign in redundant arithmetic is non-trivial. This approach retains the simplicity of a cordic datapath while eliminating the anglecomputation hardware that would normally be required. The sine and cosine of any angle in [O, 2x1 can be obtained &om those of some different angle in [O,d4] by simple negation and/or interchange operations. An arbitrary angle 0 ( < 1 radian) can be represented as e = b, + b,B, + ... + b, e, where the bi are the angle binary representation bits and 0, = 2-, radians. Notice that the et are different from those of Cordic. The b, = 1 corresponds to a rotation by 0, = 2-, radians and b, = 0 corresponds to no rotation. b,e(O,l) are recodedin signed digits r&-l,l] where r, = 2bk.1 -1. An initial fixed rotation by el = (0.5 -0.5N+i) radians is necessary to ensure equality between the two representations. After recoding, a bit b, = 1 corresponds to a positive rotation by ek = 2P-l) radians and b, = 0 corresponds to a negative rotation by 8, = 2e-l)radians. The recoding (which need not be explicitly performed) is necessary to ensure a constant scale factor K in the datapath; this is most efficiently accounted for in the algorithm implementation by starting each angle rotation sequence a t the point %= K, Yo= 0.For an N-bit output resolution, the algorithm consists of an Nstage cascade with each stage implementing a positive or negative e, subrotation (Figure 1). The subrotation stages implementation can employ the approximation tan 8,58,=2-k for sufficiently small 0, (i.e., for sficiently large k), reducing the corresponding multiplication to a simple k-bit shift operation. Given a B-bit internal word length...

A unified view for vector rotational CORDIC algorithms and architectures based on angle quantization approach

“…, for , and can be defined as (8) In Table III, we illustrate the EAS of the CORDIC with . With the help of EAS, we can say that the CORDIC algorithm essentially performs the angle quantization.…”

“…V ECTOR rotation plays an important role in many digital signal processing (DSP) applications. It is extensively employed as the processing kernel in discrete orthogonal transformations (DCT, DST, and DFT) [1]- [4], lattice-based (rotation-based) digital filtering [5], [6], sinewave/cosine generation [7], [8], and digital modulation/demodulation in communication systems [9], [10]. Let and denote the input and output vectors, respectively.…”

Field trial results for high-speed wireless indoor data communications

“…5). The demodulator takes the output of the ADC and creates the in-phase (I) and quadrature (Q) signals by using a complex multiplier driven by a quadrature direct digital frequency synthesizer (QDDFS) [17] which is part of a fully digital, high-bandwidth carrier tracking loop. The signal is then passed through a square-root-Nyquist filter with a roll-off factor of 20% and decimated by two prior to entering the adaptive equalizer.…”

Low power data converters for specific applications

“…The architecture of a conventional DDFS is originally introduced by Tiemey et al [22]. It consists of the following basic building blocks -a phase accumulator, a Recently, efforts have been made to reduce the ROM size using different compression techniques, which include the use of uigonometric identity [26], the Nicholas technique [25], the use of Taylor series [27], and the CORDIC algorithm [28]. These techniques can be used to reduce the size of the ROM significantly (32 times or more [29]).…”