A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS

A 270-MS/s 6-b SAR ADC with preamplifier sharing and self-locking comparators

“…Among these timing parts, the longest useless one is the DFF delay in the digital logic delays, T digital . In [4], the first SAR ADC with distributed comparators was proposed, as shown in Fig. 1(b).…”

“…By distributing one comparator for every comparison, the D-FF induced delay are eliminated. Thus, the critical paths delay is evolved to [4].…”

“…Given the high speed of these comparators, big kickbacks may ruin the conversion resolution. In [4], a 17x unit capacitor was inserted in the capacitive DAC to absorb the kickbacks, which degrades the input range and LSB amplitude largely. As a result, the comparator needs a tighter constraints on the offset issues and a 7-b binary DAC was applied to all the comparators to cancel these offset issues.…”

“…First, the preamplifier isolated the capacitive DAC and the comparators, and thus, kickback will not influence the charge conversation nodes. Furthermore, given that no capacitors are inserted to absorb the kickbacks and the charge conservation nodes are with less parasitic (only one-preamplifier input instead of six-comparator input), the input range and the LSB amplitude is much larger than that of [4]. The last advantage is the conventional preamplifier's benefits, fixing latches' input common mode voltages and amplifying signals fed to comparators.…”

“…Authors would like to call this effects as flashback effects. In [4], a strongARM comparator, or known as a dual cross-coupling comparator was used to reduce the possibility of these flashback effects.…”