A single-chip 1.6 billion 16-b MAC/s multiprocessor DSP

Ackland, B.; Anesko, A.; Brinthaupt, D.; Daubert, S.J.; Kalavade, A.; Knobloch, J.; Micca, E.; Moturi, M.; Nicol, C.J.; O'Neill, J.H.; Othmer, J.; Sackinger, E.; Singh, K.J.; Sweet, J.; Terman, C.J.; Williams, J.

doi:10.1109/cicc.1999.777338

Cited by 17 publications

(19 citation statements)

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“…The following example demonstrates the use of alternative sets of stubs for verification of a split transaction bus (STB) in a multiprocessor DSP [3]. An overview of the system is shown in Fig.…”

Section: Resultsmentioning

confidence: 99%

Formal verification of component-based designs

Karlsson

Eles

Peng

2007

Des Autom Embed Syst

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Embedded systems are becoming increasingly common in our everyday lives. As technology progresses, these systems become more and more complex, and designers handle this increasing complexity by reusing existing components (Intellectual Property blocks). At the same time, the systems must fulfill strict requirements on reliability and correctness.This paper proposes a formal verification methodology which smoothly integrates with component-based system-level design using a divide and conquer approach. The methodology assumes that the system consists of several reusable components, each of them already formally verified by their designers. The components are considered correct given that the environment satisfies certain properties imposed by the component. The methodology verifies the correctness of the glue logic inserted between the components and the interaction of the components through the glue logic. Each such glue logic is verified one at a time using model checking techniques.Experimental results have shown the efficiency of the proposed methodology and demonstrated that it is feasible to apply such a verification methodology on real-life examples.

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Section: Resultsmentioning

confidence: 99%

Formal verification of component-based designs

Karlsson

Eles

Peng

2007

Des Autom Embed Syst

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“…With the rapid increase of the transistor budget that is available on chips [34], DSP chip multi-processors are beginning to surface [46,47] and it is to be expected that this trend is going to continue. However, pure multi-processors suffer from the inability to share processing resources between processors.…”

Section: Architecture Requirements For Embedded Dsp Processingmentioning

confidence: 97%

A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance

Berekovic

Niggemeier

2007

J Sign Process Syst Sign Image

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A scalable, distributed, processor architecture is presented that emphasizes on high performance computing for digital signal processing applications by combining high frequency design techniques with a very high degree of parallel processing on a chip. The architecture is based on a superscalar processor model with a modified Tomasulo scheme that was extended to eliminate all central control structures for the data flow and to support simultaneous instruction issue from multiple independent threads [simultaneously multi-threaded (SMT)]. Consequent application of fine clustering reduces the cycle-time for wire-sensitive building blocks of the processor like the register file and the scheduling window and leads to a distributed architecture model, where independent thread processing units, arithmetic logic units, registers files and memories are distributed across the chip and communicate with each other by special network. A special communication protocol replaces broadcasting and associative compare of destination tags in a centralised instruction scheduler with explicit operand transfer instructions, thus decentralizing the control of the data flow to the greatest extent. As a result, the processor cycle time does neither depend on the issue bandwidth of a single thread nor on the execution bandwidth of the SMT processor. This makes the performance of the architecture scalable with both the number of function and the number of thread units without having any impact on the processors cycle-time. Performance and scalability of the proposed microarchitecture is demonstrated with critical signal processing kernels from the MPEG-4 video coding standard on a cycle-true simulator.

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“…An extension of a programmable core with dedicated modules, as, e.g., in the Trimedia [5], does not help when the functions that have been hard-wired change in a new version of a multimedia standard. Homogeneous multiprocessors offer abundant levels of raw processing power [6,7], but do not match well real-world compound multimedia processing schemes that typically involve quite diverse processing types.…”

Section: Introductionmentioning

confidence: 99%

HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing

Stolberg

Berekovic

Friebe

et al. 2005

J VLSI Sign Process Syst Sign Image Video Technol

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The HiBRID-SoC multi-core system-on-chip architecture targets a wide range of multimedia applications with particularly high processing demands, including general signal processing applications, video de-/encoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processors cores and various interfaces onto a single chip, all tied to a 64-Bit AMBA AHB bus. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The HiBRID-SoC is fabricated in a 0.18 µm 6LM standard-cell CMOS technology, occupies about 81 mm 2 , and operates at 145 MHz. An MPEG-4 Advanced Simple Profile decoder in full D1 resolution requires about 120 MHz for real-time operation on the HiBRID-SoC, utilizing only two of the three cores. Together with the third core, a custom region-of-interest (ROI) based surveillance application can be built.

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A single-chip 1.6 billion 16-b MAC/s multiprocessor DSP

Cited by 17 publications

References 0 publications

Formal verification of component-based designs

Formal verification of component-based designs

A Distributed, Simultaneously Multi-Threaded (SMT) Processor with Clustered Scheduling Windows for Scalable DSP Performance

HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing

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