A Single-Chip 25.3–28.0 GHz SiGe BiCMOS PLL with −134 dBc/Hz Phase Noise at 10 MHz Offset and −96 dBc Reference Spurs

Hickle, Mark D.; Grout, Kevin; Grens, C.M.; Flewelling, Gregory M.; Turner, S.E.

doi:10.1109/bcicts50416.2021.9682458

2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) 2021

DOI: 10.1109/bcicts50416.2021.9682458

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A Single-Chip 25.3–28.0 GHz SiGe BiCMOS PLL with −134 dBc/Hz Phase Noise at 10 MHz Offset and −96 dBc Reference Spurs

Mark D. Hickle

Kevin Grout

C.M. Grens

et al.

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Cited by 3 publications

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A Sub-Sampling 35GHz PLL in 45nm PDSOI BiCMOS with 37fs Integrated Jitter and a FoM of -252dB

Chen,

Zhang,

Chien

et al. 2024

2024 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)

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A Single-Chip 25.3–28.0 GHz SiGe BiCMOS PLL with −134 dBc/Hz Phase Noise at 10 MHz Offset and −96 dBc Reference Spurs

Cited by 3 publications

References 11 publications

A Sub-Sampling 35GHz PLL in 45nm PDSOI BiCMOS with 37fs Integrated Jitter and a FoM of -252dB

A Sub-Sampling 35GHz PLL in 45nm PDSOI BiCMOS with 37fs Integrated Jitter and a FoM of -252dB

Single-Chip 30 GHz SiGe Sub-Sampling PLL with 28.3 fs Jitter

A 59-fs-rms 35-GHz PLL with FoM of −241-dB in $0.18-\mu \mathrm{m}$ BiCMOS/SiGe Technology

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