A Single-Chip 64-Channel Ultrasound RX-Beamformer Including Analog Front-End and an LUT for Non-Uniform ADC-Sample-Clock Generation

Abstract

A 64-channel RX digital beamformer was implemented in a single chip for 3-D ultrasound medical imaging using 2-D phased-array transducers. The RX beamformer chip includes 64 analog front-end branches including 64 non-uniform sampling ADCs, a FIFO/Adder, and an on-chip look-up table (LUT). The LUT stores the information on the rising edge timing of the non-uniform ADC sampling clocks. To include the LUT inside the beamformer chip, the LUT size was reduced by around 240 times by approximating an ADC-sample-time profile w.r.t. focal points (FP) along a scanline (SL) for a channel into a piece-wise linear form. The maximum error between the approximated and accurate sample times of ADC is eight times the sample time resolution (Ts) that is 1/32 of the ultrasound signal period in this work. The non-uniform sampling reduces the FIFO size required for digital beamforming by around 20 times. By applying a 9-dot image from Field-II program and 2-D ultrasound phantom images to the fabricated RX beamformer chip, the original images were successfully reconstructed from the measured output. The chip in a 0.13-um CMOS occupies 30.25 [Formula: see text] and consumes 605 mW.

A Pitch-Matched Front-End ASIC With Integrated Subarray Beamforming ADC for Miniature 3-D Ultrasound Probes

“…The measured gain mismatch across 16 subarrays is less than 0.1 dB. Table I illustrates the comparison of this paper with the state-of-the-art digitization solutions for 3-D ultrasound imaging systems [16]- [18], [44]. Based on Table I, this work achieves a 10× improvement in power efficiency, as well as a 3.3× improvement in integration density.…”

Efficient Sample Delay Calculation for 2-D and 3-D Ultrasound Imaging

“…Some works and industrial products have focused on a low power, portable imager implementation [1]- [6], [51]. However, these systems either only support 2D imaging, or a very low channel-count 3D imaging with several major restrictions [52].…”

Towards Ultrasound Everywhere: A Portable 3D Digital Back-End Capable of Zone and Compound Imaging

“…However, its main bottleneck is the required external DRAM memory to store the BF delay coefficients, with the need of several GB/s memory bandwidth. There are also few single-FPGA US research systems, but they support up to only 64 receive channels [42], [43]. Moreover, there are many US systems relying on software-based BF, running on GPU, CPU, or DSP, but the resulting power budget is not optimal for battery operation, specially in 3D imaging.…”