A Single-chip DBS Tuner-Demodulator SoC using Discrete AGC, Continuous I/Q Correction and 200MS/s Pipeline ADCs

Maxim, A.; Poorfard, R.; Johnson, Rob; Crawley, P.J.; Kao, J.; Dong, Zhekang; Chennam, M.; Nutt, T.; Trager, D.

doi:10.1109/rfic.2007.380935

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2008

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“…As a result, widebandwidth integer-N PLLs can be used, reducing the channel switching time and over-all complexity of the system [1].…”

Section: Introductionmentioning

confidence: 99%

A 52mW 10b 210MS/s two-step ADC for digital-IF receivers in 0.13μm CMOS

Cao

Yan

2008

2008 IEEE Custom Integrated Circuits Conference

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A 10b 210MS/s two-step ADC has been implemented in 0.13µm digital CMOS with an active area of 0.38mm 2 . Using a proposed capacitor network implemented with small value interconnect capacitors which replaces the resistor ladder/multiplexer in conventional sub-ranging ADCs, and proposed offset canceling comparators, it achieves 74dB SFDR/55dB SNDR for 10MHz and 71dB SFDR/52dB SNDR for 100MHz inputs at 210MS/s while consuming 52mW from a 1.2V supply. 12-5-2

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“…As a result, widebandwidth integer-N PLLs can be used, reducing the channel switching time and over-all complexity of the system [1].…”

Section: Introductionmentioning

confidence: 99%