2004
DOI: 10.1109/jssc.2004.836349
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A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11a/b/g wireless LAN

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Cited by 118 publications
(44 citation statements)
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“…Instead, the second local oscillator (LO) frequency is derived from the first by frequency division [12], [32].…”
Section: A Superheterodyne Receivermentioning
confidence: 99%
“…Instead, the second local oscillator (LO) frequency is derived from the first by frequency division [12], [32].…”
Section: A Superheterodyne Receivermentioning
confidence: 99%
“…1 [18], [20], [21]. The received signal passes through a band-select filter and a low-noise amplifier (LNA).…”
Section: B Receivermentioning
confidence: 99%
“…7). F delay is determined for rooms A and B (Table II) using the analytical method: (21), where τ r and I diff are determined from the APDP (Table I). For room B, the values of τ r and I diff corresponding to D CP = 400 ns are also used for D CP = 800 ns.…”
Section: B Validation With Respect To the Concept Of An Effective Awgnmentioning
confidence: 99%
“…Note that RF transceiver chip includes a 6-bit digital-to-analog converter (DAC) and 4-bit I/Q analog-to-digital converters (ADCs). The receiver adopts zero-IF architecture to have low power consumption, low cost and small size (M. Valla et al (2005), Ilku-Nam et al (2003), Kwang-Jin Koh et al (2004), M. Zargari et al (2004), S. F. R. Chang et al (2005), W. Hioe et al (2004). The RF front-end circuits of receiver are shown in Fig.3.…”
Section: The Radio System Architecture For Wireless Sensor Networkmentioning
confidence: 99%