Abstract:This brief presents a single-electron injection device for position-based charge qubit structures implemented in 22 nm FD-SOI CMOS. Quantum dots are implemented in local well areas separated by tunnel barriers controlled by gate terminals overlapping with a thin 5 nm undoped silicon film. Interface of the quantum structure with classical electronic circuitry is provided with single-electron transistors that feature doped wells on the classic side. A small 0.7×0.4 µm 2 elementary quantum core is co-located with… Show more
“…Fig. 1 presents an overview of the CMOS position-based charge qubit structure containing an array of QDs [9], [11], [12], with schematics of nearby interfacing circuitry: reset, control, singleelectron injector, and detector. It is part of a quantum processor implemented in 22-nm FDSOI CMOS and operating at cryogenic temperature of 3.4 K, whose earlier version was presented in [10].…”
Section: A Imposer/injector Topologymentioning
confidence: 99%
“…Our proposed quantum processor unit (QPU) uses on-chip interface circuitry to electrostatically set the quantum states of position-based charge qubits in accordance with a given quantum algorithm [9]- [12]. These proposed quantum states are controlled by adjusting potential barriers between quantum dots (QDs) to establish, via tunneling and entanglement, the intended functions of quantum gates.…”
Section: Introductionmentioning
confidence: 99%
“…This demands high-speed voltage pulses with fine amplitude and width resolution, complexity of which grows with the QD array (QDA) structure size. In contrast with the spin-based qubit interfaces that require wide bandwidth circuitry operating at microwaves [4], the charge-based qubits can be electrostatically interfaced with baseband pulses [10], [12]. Furthermore, although the charge qubits are known to suffer from the relatively short decoherence time (50 ns to 1 µs), the ultra-high transition frequency f T in advanced CMOS can help to fit over a thousand quantum gate operations within the useful decoherence duration [9].…”
Section: Introductionmentioning
confidence: 99%
“…As a solution, we exploit the nearby single-electron detector in a test loopback configuration. A concurrent letter [12] covers some theoretical aspects of the implemented QDA structure and primarily focuses on injecting single electrons into the QDs. This CDAC is one of the key blocks used for that purpose.…”
This letter presents a fully integrated interface circuitry with a position-based charge qubit structure implemented in 22-nm FDSOI CMOS. The quantum structure is controlled by a tiny capacitive DAC (CDAC) that occupies 3.5×45 µm 2 and consumes 0.27 mW running at a 2-GHz system clock. The state of the quantum structure is measured by a single-electron detector that consumes 1 mW (including its output driver) with an area of 40×25 µm 2 . The low power and miniaturized layout of these circuits pave the way for integration in a large quantum core with thousands of qubits, which is a necessity for practical quantum computers. The CDAC output noise of 12 µV-rms is estimated through mathematical analysis while the ≤ 0.225 mV-rms input referred noise of the detector is verified by measurements at 3.4 K. The functionality of the system and performance of the CDAC are verified in a loopback mode with the detector sensing the CDAC-induced electron tunneling from the floating diffusion node into the quantum structure.
“…Fig. 1 presents an overview of the CMOS position-based charge qubit structure containing an array of QDs [9], [11], [12], with schematics of nearby interfacing circuitry: reset, control, singleelectron injector, and detector. It is part of a quantum processor implemented in 22-nm FDSOI CMOS and operating at cryogenic temperature of 3.4 K, whose earlier version was presented in [10].…”
Section: A Imposer/injector Topologymentioning
confidence: 99%
“…Our proposed quantum processor unit (QPU) uses on-chip interface circuitry to electrostatically set the quantum states of position-based charge qubits in accordance with a given quantum algorithm [9]- [12]. These proposed quantum states are controlled by adjusting potential barriers between quantum dots (QDs) to establish, via tunneling and entanglement, the intended functions of quantum gates.…”
Section: Introductionmentioning
confidence: 99%
“…This demands high-speed voltage pulses with fine amplitude and width resolution, complexity of which grows with the QD array (QDA) structure size. In contrast with the spin-based qubit interfaces that require wide bandwidth circuitry operating at microwaves [4], the charge-based qubits can be electrostatically interfaced with baseband pulses [10], [12]. Furthermore, although the charge qubits are known to suffer from the relatively short decoherence time (50 ns to 1 µs), the ultra-high transition frequency f T in advanced CMOS can help to fit over a thousand quantum gate operations within the useful decoherence duration [9].…”
Section: Introductionmentioning
confidence: 99%
“…As a solution, we exploit the nearby single-electron detector in a test loopback configuration. A concurrent letter [12] covers some theoretical aspects of the implemented QDA structure and primarily focuses on injecting single electrons into the QDs. This CDAC is one of the key blocks used for that purpose.…”
This letter presents a fully integrated interface circuitry with a position-based charge qubit structure implemented in 22-nm FDSOI CMOS. The quantum structure is controlled by a tiny capacitive DAC (CDAC) that occupies 3.5×45 µm 2 and consumes 0.27 mW running at a 2-GHz system clock. The state of the quantum structure is measured by a single-electron detector that consumes 1 mW (including its output driver) with an area of 40×25 µm 2 . The low power and miniaturized layout of these circuits pave the way for integration in a large quantum core with thousands of qubits, which is a necessity for practical quantum computers. The CDAC output noise of 12 µV-rms is estimated through mathematical analysis while the ≤ 0.225 mV-rms input referred noise of the detector is verified by measurements at 3.4 K. The functionality of the system and performance of the CDAC are verified in a loopback mode with the detector sensing the CDAC-induced electron tunneling from the floating diffusion node into the quantum structure.
“…In this paper, we have chosen an example of a quantum dot array recently implemented in a CMOS technology together with their interface electronics [22], [35]. We propose and discuss in detail a modeling methodology particularly focused on the side of the problem that may be appealing to readers with background in circuit design.…”
Quantum computers comprising large‐scale arrays of qubits will enable complex algorithms to be executed to provide a quantum advantage for practical applications. A prerequisite for this milestone is a power‐efficient qubit control and detection system operating at cryogenic temperatures. Implementing such systems in complementary metal‐oxide‐semiconductor (CMOS) technology offers clear advantages in terms of scalability. Here, we present a fully integrated quantum dot array in which silicon quantum wells are co‐located with control and detection circuitry on the same die in a commercial 22‐nm fully depleted silicon‐on‐insulator (FDSOI) process. Our system comprises a two‐dimensional quantum dot array, integrated with 8 detectors and 32 injectors, operating at 3 K inside a cryo‐cooler. The power consumption of the control and detection circuitry is 2.5 mW per qubit without body biasing. The design utilizes 0.8‐V nominal devices. The setup allows us to verify discrete charge injection control and detection at the quantum dot array and demonstrate the feasibility of this architecture for scaling up the existing quantum core to hundreds and thousands of physical qubits.
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