A Single-Ended Low Power 16-nm FinFET 6T SRAM Design With PDP Reduction Circuit

Wang, Chua‐Chin; Sangalang, Ralph Gerard B.; Tseng, I‐Ting

doi:10.1109/tcsii.2021.3123676

Cited by 6 publications

References 17 publications

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A 1.0 fJ energy/bit single‐ended 1 kb 6T SRAM implemented using 40 nm CMOS process

Wang

Sangalang

Tseng

et al. 2023

IET Circuits, Devices & Syst

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An ultra-low-energy SRAM composed of single-ended cells is demonstrated on silicon in this investigation. More specifically, the supply voltages of cells are gated by wordline (WL) enable, and the voltage mode select (VMS) signals select one of the corresponding supply voltages. A lower voltage is selected to maintain stored bit state when cells are not accessed, lowering the standby power. And when selecting a cell (i.e. WL is enabled) to perform the read or write (R/W) operations, the normal supply voltage is used. A 1-kb SRAM prototype based on the single-ended cells with built-in self-test (BIST) and powerdelay production (PDP) reduction circuits was realised on silicon using 40-nm CMOS technology. Theoretical derivations and simulations of all-PVT-corner variations are also disclosed to justify low energy performance. Physical measurements of six prototypes on silicon shows that the energy per bit is 1.0 fJ at the 10 MHz system clock. K E Y W O R D Sdigital integrated circuits, logic design, low-power electronics, memory architecture, VLSIThis is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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