A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface

Chi, Hyung-Joon; Lee, Jae Seung; Jeon, Seong-Hwan; Bae, Seung-Jun; Sohn, Young-Soo; Sim, Jae‐Yoon; Park, Hong-June

doi:10.1109/jssc.2011.2136590

Cited by 26 publications

(6 citation statements)

References 18 publications

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“…4). To increase the half-rate operating speed of RX up to 4 Gbps, a modified sense-amplifier based flip-flop [16] is used in this work. The offset calibration is performed by a (Fig.…”

Section: Rx Comparatormentioning

confidence: 99%

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface

Lee

Lim

et al. 2016

IEEE J. Solid-State Circuits

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A four-bit four-wire four-level (4B4W4L) singleended parallel transceiver for the point-to-point DRAM interface achieved a peak reduction of ∼10 dB in the electromagnetic interference (EMI) H-field power, compared to a conventional 4-bit parallel binary transceiver with the same output driver power of transmitter (TX) and the same input voltage margin of receiver (RX). A four-level balanced coding is used in this work to minimize the simultaneous switching noise at TX, to utilize a differential sensing without a reference voltage at RX, to maintain the pin efficiency of 100%, and also to reduce EMI by setting the sum of currents through the four wires to be zero. A capacitive pre-emphasis scheme modified for four-level signaling is also used at TX to compensate for inter-symbol interference. The transmitted four-level signals are recovered by six differential comparators with an offset compensation and a decoder at RX. The proposed transceiver chip fabricated in a 65 nm CMOS process consumes 2.39 pJ/bit with a 1.2 V supply and a 2 inch FR4 channel at 8 Gb/s. Index Terms-Balanced coding, DRAM interface, electromagnetic interference (EMI), H-field measurement, parallel links, single-ended, transceiver, 4-bit 4-wire 4-level signaling.

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“…4). To increase the half-rate operating speed of RX up to 4 Gbps, a modified sense-amplifier based flip-flop [16] is used in this work. The offset calibration is performed by a (Fig.…”

Section: Rx Comparatormentioning

confidence: 99%

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface

Lee

Lim

et al. 2016

IEEE J. Solid-State Circuits

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“…Even in such rare cases where the transmissive medium is well known, the design itself is intrinsically dependent on process, voltage and temperature (PVT) variations and technology corners, all of which need to be counteracted by the equalizers. Therefore, calibration and adaptation strategies are required in order to find the optimal equalization parameters for the actual channel [13,[15][16][17]. Full adaptation automatically performs such a task, and is usually implemented in the form of Sign-Sign Least-Mean Squares (SS-LMS) algorithms due to the short time required to adjust the equalization parameters and the simplicity of their realization [11,12,15,16,[18][19][20][21].…”

Section: Introductionmentioning

confidence: 99%

A Simple Modelling Tool for Fast Combined Simulation of Interconnections, Inter-Symbol Interference and Equalization in High-Speed Serial Interfaces for Chip-to-Chip Communications

Menin¹,

Bernardi²,

Cortiula³

et al. 2020

Adv. sci. technol. eng. syst. j.

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We describe an efficient system-level simulator that, starting from the architecture of a well-specified transmissive medium (a channel modelled as single-ended or coupled differential microstrips plus cables) and including the system-level characteristics of transmitter and receiver (voltage swing, impedance, etc.), computes the eye diagram and the bit-error rate that is obtained in high-speed serial interfaces. Various equalization techniques are included, such as feed-forward equalization at the transmitter, continuous-time linear equalization and decision-feedback equalization at the receiver. The impact of clock and data jitter on the overall system performance can easily be taken into account and fully-adaptive equalization can be simulated without increasing the computational burden or the model's complexity.

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“…For the DFE adaptation, Sign-to-sign least mean square (SS-LMS) algorithm has been widely used with a digital signal processor [8], [9]. To reduce the area overhead of the DFE adaptation circuits, a single loop SS-LMS algorithm has been presented in [10], but it still requires additional paths for intersymbol interference (ISI) detector and a finite-state machine at the cost of the power consumption and area. Hence, using two dedicated ALs for each CTLE and DFE increases the complexity and power consumption of the receiver.…”

Section: Introductionmentioning

confidence: 99%

A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method

Kim

Lee

Kim

2016

IEEE Trans. VLSI Syst.

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This brief presents an adaptive continuous-time linear equalizer (CTLE) and one-tap decision feedback equalizer (DFE) using the spectrum balancing (SB) method. The SB method is extended for not only CTLE but also DFE with the aid of gain characteristics of one-tap DFE. Thus, adaptation loops for each equalizer type are merged to a single loop. As a result, the complexity and power consumption of the adaptation circuits are reduced significantly. The test chip consumes 34.2 mW from 1.2 V supply with 65-nm CMOS process. Index Terms-Adaptation, continuous-time linear equalizers (CTLEs), decision feedback equalizers (DFEs), equalizer, intersymbol interference (ISI), single loop.1063-8210

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A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface

Cited by 26 publications

References 18 publications

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface

A Simple Modelling Tool for Fast Combined Simulation of Interconnections, Inter-Symbol Interference and Equalization in High-Speed Serial Interfaces for Chip-to-Chip Communications

A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method

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