A single-path pulsewidth control loop with a built-in delay-locked loop

Han, Sung-Rung; Liu, Shen-Iuan

doi:10.1109/jssc.2005.845988

Cited by 25 publications

(2 citation statements)

References 6 publications

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“…to design the delay network [20][21]. First time we are designed the delay network using the DPDE such as Current starved inverter (CSI) element by taking non-linearity's into consideration [22], to enhance the metrics of the PUF circuit. CSI is core of the arbiter PUF architecture, which acts like a switch and controls the delay characteristics of the PUF circuit.…”

Section: Digitally Programmable Delay Element (Dpde)mentioning

confidence: 99%

Design of a Reliable Current Starved Inverter Based Arbiter Physical Unclonable Functions (PUFs) for Hardware Cryptography

Kurra¹,

Nelakuditi²

2019

ISI

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For most cryptographic algorithms, the secret keys must be permanently stored in nonvolatile memories (NVNs) and used for distinct security operations. This gives rise to power constraints, location limits and security threats to hardware facilities. To solve the problems, this paper proposes a novel and reliable current starved inverter (CSI) based on a physical unclonable function (PUF) architecture (8, 16 and 32 stages), using 45nm complementary metal-oxide-semiconductor (CMOS) technology. The proposed CSI was simulated on Spectre Simulation Platform. The results show that its uniqueness, reliability and randomness were 49.26 %, 98.86 % and 86.12 %, respectively, in the temperature range of-20~80 ℃. In addition, the performance of the proposed CSI was proved to outshine that of existing PUF architectures in stability and reliability. The research results are significant for the development of critical security applications.

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Section: Digitally Programmable Delay Element (Dpde)mentioning

confidence: 99%

Design of a Reliable Current Starved Inverter Based Arbiter Physical Unclonable Functions (PUFs) for Hardware Cryptography

Kurra¹,

Nelakuditi²

2019

ISI

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“…Moreover, digital circuitry were designed and incorporated in the FS to adjust clock duty cycles, which are needed in applications such as time-interleaved ADCs, switchedcapacitor circuits, and DC-DC converters [12][13][14]. The concept and the preliminary simulation result of the proposed technique were first introduced in [15]; the detailed silicon implementation and measurement results of the above FS will be demonstrated in this paper.…”

Section: Introductionmentioning

confidence: 99%

An instant-switching ∆–Σ fractional-N frequency synthesizer with adjustable duty cycles

Huang

Gui

Fan

et al. 2011

Analog Integr Circ Sig Process

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A Phase-Locked Loop (PLL)-based frequency synthesizer (FS) with adjustable duty cycle is presented. By employing digital processing circuitry and the D-R fractional-N technique, the FS is capable of generating arbitrary frequencies in a wide frequency range, and capable of adjusting the clock duty cycles. In addition, the switching between different frequencies is instant except when a very fine frequency resolution is required. The adjustable duty cycle and instant switching are desired features in applications such as time-interleaved Analog-to-DigitalConverters (ADCs), switched-capacitor circuits, and DC-DC converters. The design was fabricated using a 0.13 lm CMOS process. This paper gives the theories, analysis, implementation, and measurement results of this FS.

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