2012
DOI: 10.1109/led.2012.2187420
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A Single-Photon Avalanche Diode in 90-nm CMOS Imaging Technology With 44% Photon Detection Efficiency at 690 nm

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Cited by 104 publications
(72 citation statements)
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“…Future research activity in this area will be aimed at the development of denser arrays with larger formats (>10 6 pixels) by exploiting sub-100 nm CMOS technologies [101]. It appears likely that large CMOS SPAD arrays of the type discussed here but with improved sensitivity [102], coupled to microlens arrays [109] or designed to achieve fill factors close to 100% by alternative architectures, will play an important role in time-resolved photon-counting imaging.…”
Section: Discussionmentioning
confidence: 99%
See 1 more Smart Citation
“…Future research activity in this area will be aimed at the development of denser arrays with larger formats (>10 6 pixels) by exploiting sub-100 nm CMOS technologies [101]. It appears likely that large CMOS SPAD arrays of the type discussed here but with improved sensitivity [102], coupled to microlens arrays [109] or designed to achieve fill factors close to 100% by alternative architectures, will play an important role in time-resolved photon-counting imaging.…”
Section: Discussionmentioning
confidence: 99%
“…SPAD devices have been demonstrated in 90 nm CMOS technologies, but with significantly lower performance [101]. A notable exception is the 90 nm SPAD device reported by Webster et al [102], where the deep n-well/p-epi junction is used as the active junction, achieving a peak PDE of 44 % at 690 nm and better than 20 % at 850 nm. Timing jitter as low as 50 ps FWHM was demonstrated, although the timing distribution was affected by a relatively long diffusion tail.…”
Section: Available Spad Technologiesmentioning
confidence: 99%
“…State-of-the-art SPAD technology has reached the 90nm CMOS technology node [4], [5]. In this paper, we propose a new APD fully characterized and modeled in a standard 65nm CMOS process that operates in Geiger and proportional mode.…”
Section: Introductionmentioning
confidence: 99%
“…Advanced SPAD array manufacturing techniques such as 3D stacking are expected to push fill-factor and spatial resolution to comparable levels to incumbent technologies such as sCMOS or EMCCD whilst offering picosecond time resolution. Recent developments in CMOS SPAD technology have shown significant improvements in many features [145], such as the dead time [146], dark count [142,147], pixel miniaturization [148], and quantum efficiency in the longer wavelength region [149]. It is expected high resolution CMOS SPAD arrays for ranging applications (Geiger mode light detection and ranging (LIDAR)) [137,150] will soon be applied to FLIM.…”
Section: Spad Arraysmentioning
confidence: 99%