A Single Program Multiple Data Parallel Processing Platform for FPGAs

James-Roxby, Philip; Schumacher, P.; Ross, Charlie

doi:10.1109/fccm.2004.9

Cited by 20 publications

(17 citation statements)

References 4 publications

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“…They use Xilinx MicroBlaze processor for the core, and a bus protocol for the inter-core communication. James-Roxby et al [12] shows similar FPGA design in their proposed architecture for supporting a single program multiple data model of parallel processing.…”

Section: Related Workmentioning

confidence: 99%

Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System

Kinsy

Pellauer

Devadas

2011

2011 21st International Conference on Field Programmable Logic and Applications

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Heracles is an open-source complete multicore system written in Verilog. It is fully parameterized and can be reconfigured and synthesized into different topologies and sizes. Each processing node has a 7-stage pipeline, fully bypassed, microprocessor running the MIPS-III ISA, a 4-stage inputbuffer, virtual-channel router, and a local variable-size shared memory. Our design is highly modular with clear interfaces between the core, the memory hierarchy, and the on-chip network. In the baseline design, the microprocessor is attached to two caches, one instruction cache and one data cache, which are oblivious to the global memory organization. The memory system in Heracles can be configured as one single global shared memory (SM), or distributed shared memory (DSM), or any combination thereof. Each core is connected to the rest of the network of processors by a parameterized, realistic, wormhole router. We show different topology configurations of the system, and their synthesis results on the Xilinx Virtex-5 LX330T FPGA board. We also provide a small MIPS cross-compiler toolchain to assist in developing software for Heracles.

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Section: Related Workmentioning

confidence: 99%

Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System

Kinsy

Pellauer

Devadas

2011

2011 21st International Conference on Field Programmable Logic and Applications

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“…Clark et al [2] and James-Roxby et al [6] present architectures that use shared memory only for data, while multiple programs must reside locally in the processor memory. Furthermore, ad hoc programming techniques are used to deal with synchronization of shared resources, lacking of a real systematic approach.…”

Section: Related Workmentioning

confidence: 99%

A design kit for a fully working shared memory multiprocessor on FPGA

Tumeo

Monchiero

Palermo

et al. 2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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This paper presents a framework to design a shared memory multiprocessor on a programmable platform. We propose a complete flow, composed by a programming model and a template architecture. Our framework permits to write a parallel application by using a shared memory model. It deals with the consistency of shared data, with no need of hardware coherence protocol, but uses a software model to properly synchronize the local copies with the shared memory image. This idea can be applied both to a scratchpadbased architecture or a cache-based one. The architecture is synthesizable with standard IPs, such as the softcores and interconnect elements, which may be found in any commercial FPGA toolset.

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“…The application chosen for benchmarking is the JPEG2000 image compression standard algorithm [18]. The JPEG2000 is commonly used as a reference benchmark for multiprocessor systems [19] and for multiprocessor implementations on FPGA [20]. It is an evolution of the previous JPEG standard, in which the main compression phase is performed through a Discrete Wavelet Transform (DWT) instead of the Discrete Cosine Transform (DCT).…”

Section: Case Study: the Jpeg 2000mentioning

confidence: 99%

A multiprocessor self-reconfigurable JPEG2000 encoder

Tumeo

Borgio

Bosisio

et al. 2009

2009 IEEE International Symposium on Parallel &Amp; Distributed Processing

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Abstract-This paper presents a multiprocessor architecture prototype on a Field Programmable Gate Arrays (FPGA) with support for hardware and software multithreading. Thanks to partial dynamic reconfiguration, this system can, at run time, spawn both software and hardware threads, sharing not only the general purpose soft-cores present in the architecture but also area on the FPGA. While on a standard single processor architecture the partial dynamic reconfiguration requires the processor to stop working to instantiate the hardware threads, the proposed solution hides most of the reconfiguration latency through the parallel execution of software threads. We validate our framework on a JPEG 2000 encoder, showing how threads are spawned, executed and joined independently of their hardware or software nature. We also show results confirming that, by using the proposed approach, we are able to hide the reconfiguration time.

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A Single Program Multiple Data Parallel Processing Platform for FPGAs

Cited by 20 publications

References 4 publications

Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System

Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System

A design kit for a fully working shared memory multiprocessor on FPGA

A multiprocessor self-reconfigurable JPEG2000 encoder

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