A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability

Seo, Min-Jae; Jin, Dayong; Kim, Ye-Dam; Kim, Jong-Pal; Chang, Dong Jin; Lim, Won-Mook; Chung, Jaywan; Park, Chang-Un; An, Eun-Ji; Ryu, Seung‐Tak

doi:10.1109/a-sscc47793.2019.9056894

Cited by 6 publications

(1 citation statement)

References 1 publication

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“…The analog outputs of two readout channels are multiplexed to one ADC using the ADC input MUX control signal (f_MUX). The ADC has a 12-bit asynchronous successive approximation (SAR) type and oversamples 8 times to achieve 15-bit resolution using the ADC conversion control signal (f_ADC) [5]. header representing the data packet.…”

Section: Circuit Architecture and Designmentioning

confidence: 99%

A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section

Kim

Lee

Suh

et al. 2020

2020 42nd Annual International Conference of the IEEE Engineering in Medicine &Amp; Biology Society (EMBC)

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A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC is presented for the application of local activation imaging in nerve section. It is increasingly known that the monitoring and control of nerve signals can improve physical and mental health. Major nerves, such as the vagus nerve and the sciatic nerve, consist of a bundle of fascicles. Therefore, to accurately control a particular application without any side effects, we need to know exactly which fascicle was activated. The only way to find locally activated fascicle is to use electrical impedance tomography (EIT). The ASIC to be introduced is designed for neural EIT applications. A neural impedance sensing ASIC was implemented using CMOS 180-nm process technology. The integrated input referred noise was calculated to be 0.46 μVrms (noise floor 10.3 nVrms/rt Hz) in the measured noise spectrum. At an input of 80 mV, the squared correlation coefficient for linear regression was 0.99998. The amplification gain uniformity of 32 channels was in the range of + 0.23% and -0.29%. Using the resistor phantom, the simplest model of nerve, it was verified that a single readout channel could detect a signal-to-noise ratio of 75.6 dB or more. Through the reservoir phantom, real-time EIT images were reconstructed at a rate of 8.3 frames per second. The developed ASIC has been applied to in vivo experiments with rat sciatic nerves, and signal processing is currently underway to obtain activated nerve cross-sectional images. The developed ASIC was also applied to in-vivo experiments with rat sciatic nerves, and signal processing is currently underway to obtain locally activated nerve cross-sectional images.Clinical Relevance-This introduces a tool for non-invasive viewing of locally activated fascicles in a nerve cross section.

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Section: Circuit Architecture and Designmentioning

confidence: 99%

A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section

Kim

Lee

Suh

et al. 2020

2020 42nd Annual International Conference of the IEEE Engineering in Medicine &Amp; Biology Society (EMBC)

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Open-source design of integrated circuits

Fath,

Moser,

Zachl

et al. 2024

Elektrotech. Inftech.

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This paper presents the design of a self-clocked 12-bit non-binary fully differential SAR-ADC using the SKY130 open-source PDK. The entire mixed-signal circuit design and layout were created with free and open-source software. The ADC reaches a sample rate of up to 1.44 MS/s at 1.8 V supply while consuming 703 $$\upmu$$ μ W of power on a small 0.175 mm$${}^{2}$$ 2 area. A configurable decimation filter can increase the ADC resolution up to 16 bits while using an oversampling factor of 256. A 9‑bit thermometer-coded and 3‑bit binary-coded DAC matrix using a 448 aF waffle-capacitor results in a total capacitance of 1.83 pF per input. Realizations of configurable analog functions using the form factor of SKY130 high-density standard cells allow the parametrization of an analog circuit in a hardware description language and hardening of the macro in an intentionally digital workflow.

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An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation

Lim

Mabilangan

Chang

et al. 2021

2021 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability

Cited by 6 publications

References 1 publication

A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section

A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section

Open-source design of integrated circuits

An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation

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