A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability

Seo, Min-Jae; Jin, Dayong; Kim, Ye-Dam; Kim, Jong-Pal; Ryu, Seung‐Tak

doi:10.1109/jssc.2020.3006450

Cited by 11 publications

(4 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The 1st-stage SAR ADC consists of 9-bit non-binary (8b full-binary equivalent) CDACs, two 8-bit CDACs to generate additional reference signals, the bootstrapped switches in [24] and SAR control logic. Figure 13 depicts the simulated differential nonlinearity (DNL) and integrated nonlinearity (INL).…”

Section: St-stage Adc: Multi-bit Sar Adc With Background Calibrationmentioning

confidence: 99%

A Single-Amplifier Dual-Residue Pipelined-SAR ADC

Seo

2021

Electronics

Self Cite

View full text Add to dashboard Cite

This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two residue levels from the single RA, which eliminates the need for inter-stage gain-matching calibration. To convert the sequentially generated the two residues, a capacitive interpolating SAR ADC (I-SAR ADC) is also proposed. The I-SAR ADC is very compact because it consists of the one comparator, a CDAC, and control logic like a conventional SAR ADC. In addition, the I-SAR ADC needs no static power dissipation for the residue interpolation. A prototype ADC fabricated in a 40 nm CMOS technology occupies an active area of 0.026 mm2. At a 200 MS/s sampling-rate with the Nyquist input, the ADC achieves an SNDR (Signal-to-Noise distortion ratio) of 62.1 dB and 67.1 dB SFDR (Spurious-Free Dynamic Range), respectively. The total power consumed is 3.9 mW under a 0.9 V supply. Without any inter-stage mismatch calibration, the ADC achieve Walden Figure-of-Merit (FoM) of 19.0 fJ/conversion-step.

show abstract

Section: St-stage Adc: Multi-bit Sar Adc With Background Calibrationmentioning

confidence: 99%

A Single-Amplifier Dual-Residue Pipelined-SAR ADC

Seo

2021

Electronics

Self Cite

View full text Add to dashboard Cite

show abstract

“…The temperature estimation function of this type of time domain CMOS temperature sensor is defined as the ratio of two different temperature dependent delay times. The typical structure of this type of temperature sensor, which was proposed by P. Chen et al in 2010 [38], includes two delay lines, of which delay times vary in a different way from each other with respect to temperature, and a successive approximation register (SAR) control logic [76][77][78][79][80][81][82][83][84][85][86][87] implemented as an FSM. For example, if one of these delay lines is composed of the general inverter type delay cells of Figure 5b, then the other is composed of the delay cells shown in Figure 6b which are less sensitive to temperature [33,38].…”

Section: Typementioning

confidence: 99%

Categorization and Characterization of Time Domain CMOS Temperature Sensors

Byun

2020

Sensors

View full text Add to dashboard Cite

Time domain complementary metal-oxide-semiconductor (CMOS) temperature sensors estimate the temperature of a sensory device by measuring the frequency, period and/or delay time instead of the voltage and/or current signals that have been traditionally measured for a long time. In this paper, the time domain CMOS temperature sensors are categorized into twelve types by using the temperature estimation function which is newly defined as the ratio of two measured time domain signals. The categorized time domain CMOS temperature sensors, which have been published in literature, show different characteristics respectively in terms of temperature conversion rate, die area, process variation compensation, temperature error, power supply voltage sensitivity and so on. Based on their characteristics, we can choose the most appropriate one from twelve types to satisfy a given specification.

show abstract

“…A 50% increase in output range improves SNR by 3.5dB, resulting in a 0.6bit increment in the equivalent number of bits (ENOB). This improvement makes sense in a high-resolution ADC [7,8]. What's more, the high output range facilitates high-quality signals in applications like SC filters [9,10], modulators [11,12,13,14], and et al [15,16,17].…”

Section: Introductionmentioning

confidence: 99%

A 2.5-Vpp PVT-insensitive high dynamic range output stage using bulk voltages adjustment

Liu

Chen

Tang

2022

IEICE Electron. Express

View full text Add to dashboard Cite

This paper presents a process, voltage, and temperature (PVT)insensitive high dynamic range output stage for switched-capacitor (SC) circuits. A new technique of constant threshold voltages using bulk voltages adjustment is presented to realize the output stage with the N and P-type (N-P) complementary transistors. Boosting circuits are used to generate bulk voltages higher than the supply voltage or lower than the ground voltage. The stability of the bulk loop consisting of a boosting circuit, an amplifier, and a replica transistor is studied. This design is implemented in TSMC 0.18𝜇m technology. Simulation results show that the output stage can achieve a differential dynamic range of 2.5Vpp, obtaining a significant 47% improvement.

show abstract

A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability

Cited by 11 publications

References 15 publications

A Single-Amplifier Dual-Residue Pipelined-SAR ADC

A Single-Amplifier Dual-Residue Pipelined-SAR ADC

Categorization and Characterization of Time Domain CMOS Temperature Sensors

A 2.5-Vpp PVT-insensitive high dynamic range output stage using bulk voltages adjustment

Contact Info

Product

Resources

About