A single TSV-rail 3D quasi delay insensitive asynchronous signaling

Abstract

Asynchronous communications are foreseen as mandatory for implementing 3D multiple tiers circuits. The drawback of asynchronous rails compared to synchronous ones is the higher number of interconnects. This number needs to be decreased when horizontal interconnects are replaced by Through Silicon Vias (TSV) because of their big silicon footprint. A circuit using only one TSV for asynchronous, quasi delay insensitive 3D signal propagation is proposed. This achieves to save two TSVs out of three, while offering 1Gbits/s capability.