A single-V/sub t/ low-leakage gated-ground cache for deep submicron

Agarwal, Amit; Li, Hai; Roy, Kaushik

doi:10.1109/jssc.2002.807414

Cited by 117 publications

(96 citation statements)

References 14 publications

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“…If the voltage on this node is raised when the cell is not accessed, the signal rail V H -V L is reduced lowering the subthreshold leakage current. In order to raise the voltage of node L and to disconnect it from the physical ground, a gated-ground NMOS transistor may be inserted in the pulldown path [2] (fig 2a). During the idle time, this transistor is off and the leakage mechanisms inside the cell are responsible for charging L. At the same time, the voltage of the node storing "0" rises as well and reaches a saturated value.…”

Section: Leakage Reduction Techniquementioning

confidence: 99%

“…The cell access delay is referred only to the discharge time of BL or BL during a reading operation and it is defined as the delay between the time at which the input signal of the wordline driver (WL' in fig 2) is V DD /2 and the voltage difference between BL and BL becomes V DD /10 [9]. Techniques [2] and [4] show an increased access delay because they both introduce an NMOS transistor in the pulldown network of the cell. For technique [2] the transition latency is zero because the delay in switching the cell into the sleep or active mode is taken into account in the cell access delay.…”

Section: Access Delay and Energy Savings Analysismentioning

confidence: 99%

“…Techniques [2] and [4] show an increased access delay because they both introduce an NMOS transistor in the pulldown network of the cell. For technique [2] the transition latency is zero because the delay in switching the cell into the sleep or active mode is taken into account in the cell access delay. In fact in [2] there is no sleep signal and the cell state (active or idle) is governed by the same WL signal.…”

Section: Access Delay and Energy Savings Analysismentioning

confidence: 99%

“…For technique [2] the transition latency is zero because the delay in switching the cell into the sleep or active mode is taken into account in the cell access delay. In fact in [2] there is no sleep signal and the cell state (active or idle) is governed by the same WL signal. So the access delay of the cell increases also due to the extra capacitive load on the WL signal.…”

Section: Access Delay and Energy Savings Analysismentioning

confidence: 99%

“…Adding extra circuits or modifying the capacitive load on the peripheral circuits that are present in a conventional SRAM structure may make a low standby power technique inadequate owing to the dynamic energy overhead it introduces during the cell access operation. Recently, many circuit techniques have been proposed [2], [3], [4]. The aim of this work is to investigate the net energy saving of these techniques taking into account their benefits in terms of static energy and their dynamic energy overheads during the write or read operation inside the cell.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Leakage energy reduction techniques in deep submicron cache memories: a comparative study

Frustaci

Corsonello

Perri

et al.

2006 IEEE International Symposium on Circuits and Systems

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Abstract-Static energy consumption due to subthreshold leakage current is one of the main concern in on-chip level-1 and level-2 cache. In the last few years several techniques have been proposed to limit the subthreshold current in a SRAM cell. Unfortunately, these techniques also increase the dynamic energy during the cell access operation, with respect to the conventional SRAM architecture. In this paper the actual energy saving offered by low leakage approaches is investigated, within the context of a microprocessor memory hierarchy, taking into account their dynamic energy overheads. Simulation based on UMC 0.18µm-1.8V and ST 90nm-1V process models have been performed. Results show that, for both the technologies, the leakage energy saving achieved by the analyzed techniques in the first cache level turns out to be inadequate, owing to the extra dynamic energy dissipation. Only in UL2 they assure a net energy saving due to the smaller number of accesses.

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Section: Leakage Reduction Techniquementioning

confidence: 99%

Section: Access Delay and Energy Savings Analysismentioning

confidence: 99%

Section: Access Delay and Energy Savings Analysismentioning

confidence: 99%

Section: Access Delay and Energy Savings Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Leakage energy reduction techniques in deep submicron cache memories: a comparative study

Frustaci

Corsonello

Perri

et al.

2006 IEEE International Symposium on Circuits and Systems

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Using Branch Prediction Information for Near-Optimal I-Cache Leakage

Chung

Skadron

2006

Advances in Computer Systems Architecture

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This paper describes a new on-demand wakeup prediction policy for instruction cache leakage control that achieves better leakage savings than prior policies, and avoids the performance overheads of prior policies. The proposed policy reduces leakage energy by more than 92% with only less than 0.3% performance overhead on average, whereas prior policies were either prone to severe performance overhead or failed to reduce the leakage energy as much. The key to this new on-demand policy is to use branch prediction information for the wakeup prediction. In the proposed policy, inserting an extra stage for wakeup between branch prediction and fetch, allows the branch predictor to be also used as a wakeup predictor without any additional hardware. Thus, the extra stage hides the wakeup penalty, not affecting branch prediction accuracy. Though extra pipeline stages typically add to branch misprediction penalty, in this case, the extra wakeup stage on the normal fetch path can be overlapped with misprediction recovery. With such consistently accurate wakeup prediction, all cache lines except the next expected cache line are in the leakage saving mode, minimizing leakage energy. We focus on super-drowsy leakage control using reduced supply voltage, because it is well suited to the instruction cache's criticality. The proposed policy can be applied to other leakage saving circuit techniques as long as the wakeup penalty is at most one cycle.

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Static Memory Design

Tzartzanis

Series on Integrated Circuits and Systems

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A single-V/sub t/ low-leakage gated-ground cache for deep submicron

Cited by 117 publications

References 14 publications

Leakage energy reduction techniques in deep submicron cache memories: a comparative study

Leakage energy reduction techniques in deep submicron cache memories: a comparative study

Using Branch Prediction Information for Near-Optimal I-Cache Leakage

Static Memory Design

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