Proceedings of Technical Program of 2012 VLSI Design, Automation and Test 2012
DOI: 10.1109/vlsi-dat.2012.6212590
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A slew rate self-adjusting 2×VDD output buffer With PVT compensation

Abstract: A novel PVT (Process, Voltage, Temperature) detection and compensation technique is proposed to automatically adjust the slew rate of a 2×VDD output buffer. The threshold voltage (Vth) of PMOSs and NMOSs varying with process, voltage, and temperature deviation could be detected, respectively. The proposed design is implemented using a typical 90 nm CMOS process to justify the performance. By adjusting output currents, the slew rate of output signal could be compensated over 38% and the maximum data rate with c… Show more

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Cited by 5 publications
(4 citation statements)
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“…The specific deviation values are shown in Table 2. Figures [10][11][12] show that a Monte Carlo simulation was carried out in 500 samples when VBB = 24 V, A1A2 = 00, A1A2 = 01, and A1A2 = 10 to evaluate the sensitivity of the output voltage under process variation and mismatch conditions. The worst case of the process sensitivity (σ/µ) is 0.1%.…”
Section: Simulation and Experimental Resultsmentioning
confidence: 99%
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“…The specific deviation values are shown in Table 2. Figures [10][11][12] show that a Monte Carlo simulation was carried out in 500 samples when VBB = 24 V, A1A2 = 00, A1A2 = 01, and A1A2 = 10 to evaluate the sensitivity of the output voltage under process variation and mismatch conditions. The worst case of the process sensitivity (σ/µ) is 0.1%.…”
Section: Simulation and Experimental Resultsmentioning
confidence: 99%
“…It can be seen from Equation (12) above that VCP increases continuously within t 2 . The parameters of r 1 , r 2 , C 1 , C 2 through the on-resistance Ron of the switch transistor, the pump capacitance C f , the load capacitance C L , the load resistance R L affect the charging rate in the t 2 stage.…”
Section: System Designmentioning
confidence: 96%
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