A Small-Area and Low-Power Scan Driver Using a Coplanar a-IGZO Thin-Film Transistor With a Dual-Gate for Liquid Crystal Displays

Kim, Do‐Sung; Kwon, Oh‐Kyong

doi:10.1109/led.2016.2638832

Cited by 17 publications

(6 citation statements)

References 11 publications

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“…2(b), C1 and C2 are implemented with a vertical stack structure. Different from the previous dual-gate method [14], here the ITO layer is acting as the second capacitor electrode. Both the gate insulating layer and the passivation layer are employed for capacitor dielectric.…”

Section: Resultsmentioning

confidence: 99%

Capacitor Reused Gate Driver for Compact In-Cell Touch Displays

Shen

Liao

Yang

et al. 2021

IEEE J. Electron Devices Soc.

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Section: Resultsmentioning

confidence: 99%

Capacitor Reused Gate Driver for Compact In-Cell Touch Displays

Shen

Liao

Yang

et al. 2021

IEEE J. Electron Devices Soc.

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“…The electrical properties of the device show field-effect mobility (μ FE ) of 13.2 cm 2 /Vs, subthreshold swing (SS) of 0.32 V/decade, threshold voltage (V th ) of 3.2 V, and on/off ratio of 8.8 × 10 8 and these values are reasonably good compared with the other reported experimental results for self-aligned coplanar a-IGZO TFTs. 6,8,10,18,19 To determine the device stability of self-aligned coplanar a-IGZO TFTs with DUV irradiation, we evaluated stability behavior of the device under negative bias stress (NBS), negative bias illumination stress (NBIS), positive bias stress (PBS), and positive bias temperature stress (PBTS) conditions. Figure 5 shows the transfer characteristics of TFTs as a function of time under NBS, NBIS, PBS, and PBTS conditions.…”

Section: Resultsmentioning

confidence: 99%

Stability Behavior of Self-Aligned Coplanar a-IGZO Thin Film Transistors Fabricated by Deep Ultraviolet Irradiation

Kim

Choi

Jeon

et al. 2018

ECS J. Solid State Sci. Technol.

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We fabricated self-aligned coplanar amorphous indium-gallium-zinc-oxide (a-IGZO) TFTs and defined the source/drain region using deep ultraviolet (DUV) irradiation. For our TFTs, source/drain region were well defined to designed dimensions and contact resistance was low value. The electrical properties of the device show field-effect mobility (μ FE ) of 13.2 cm 2 /Vs, subthreshold swing (S/S) of 0.32 V/decade, threshold voltage (V th ) of 3.2 V, and on/off ratio of 8.8 × 10 8 , respectively. In addition, the reduced channel length ( L) and width-normalized contact resistance (R SD W) were 1.08 μm and 87.5 cm, respectively. Stability behavior of self-aligned coplanar a-IGZO TFT fabricated by DUV irradiation was investigated under negative bias stress (NBS), negative bias illumination stress (NBIS), positive bias stress (PBS), and positive bias temperature stress (PBTS). After the stress under NBS, NBIS, PBS, and PBTS, the V th values of −0.3 V, −0.8 V, 1.2 V, and 1.3 V were measured, respectively. Additionally, the electrical characteristics of the n+ doping region by DUV irradiation were not degraded under any of the stress conditions. © The Author Amorphous oxide semiconductors (AOS) have been intensively studied as promising materials for active layer of thin film transistors (TFTs) because of their low off-current, high mobility, and good switching properties compared to amorphous silicon (a-Si)-based TFTs. Among the many oxide TFTs, amorphous In-Ga-Zn-O (a-IGZO) TFTs have been commercialized as backplanes of organic light emission display (OLED) TVs due to their high mobility. 1,2Oxide TFTs with conventional bottom-gate structures such as back channel etch (BCE) and etch-stopper layer (ESL) structure have been widely applied in display back-plane. However, these structures have high parasitic capacitance induced by overlap between gate and source/drain electrodes.3 This parasitic capacitance can generate a voltage drop, which results in brightness non-uniformity, flickering, and image lagging in flat panel displays (FPDs). Self-aligned coplanar structured TFTs are candidate next-generation FPDs because overlap between gate and source/drain electrodes can be minimized, reducing parasitic capacitance. 4,5 In previous research, we reported selfaligned coplanar a-IGZO top gate TFTs with various DUV irradiation energies. 6 The n+ doping techniques using DUV irradiation is a very simple process. In addition, the self-aligned coplanar TFTs fabricated by DUV irradiation have attractive results for reduced channel length ( L) and width-normalized contact resistance (R SD W) compared to other n+ doping methods. [6][7][8][9] We observed that the electrical properties of n+ regions were stable at elevated temperatures. However, to use these self-aligned TFTs fabricated by DUV irradiation as back planes for OLEDs, the behavior of TFT stability under various stress conditions needs to be studied. In a self-aligned coplanar structure, the electrical characteristics of the n+ doping region formed by diffusion of hydrogen or/...

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“…Nowadays gate driver integration using thin-film transistors(TFTs) has been a mainstream in high-end active matrix displays due to the merits of decreased peripheral driver chips, narrower display bezel with simplified module process, and reduced manufacturing cost [1]- [4]. However, implementations of TFTs integrated gate-driver for higher resolution display with large panel size become increasingly challenging [5]- [7]. This is because the effective addressing time of gate-lines is limited and pixel charging ratio is insufficient due to the increase of loading resistance and capacitance at gate driver's output electrodes [8].…”

Section: Introductionmentioning

confidence: 99%

A-Si TFT Integrated Gate Driver Workable at −40°C Using Bootstrapped Carry Signal

et al. 2022

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A thin-film transistors (TFTs) integrated gate driver which can work well at low temperature down to -40 • C is proposed and demonstrated. The carry signal (CN) of the driver, being generated through the voltage bootstrapping approach using a CN-connected capacitor, is used to pre-charge the following stage of the driver. As the rising and falling time of CN is much shorter than that of the gate driving signal GN, the bootstrapping voltage is increased and voltage loss of the pre-charge transistor can be much reduced, to avoid the driver's malfunction at low temperature. This structure further benefits maintaining the driving speed over long operation time at high temperature. On the other hand, the GN, instead of CN, is used to reset the gate driver to suppress the voltage feed-through effects. One single stage of the driver consists of 11 TFTs and 2 capacitors, driven by 4 clock signals with the duty ratio of 25%. An a-Si:H TFTs implemented single stage circuit of the driver occupies an area of 250 μm×1099 μm. Measurements show that the output voltage magnitude can be maintained well when temperature varies from -40 • C to 80 • C. Moreover, the rising-time and falling-time increase of the output pulse are both less than 3 μs after 240 hours of the accelerated high temperature aging operations.INDEX TERMS a-Si TFT; gate driver circuit; reliability; low temperature

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A Small-Area and Low-Power Scan Driver Using a Coplanar a-IGZO Thin-Film Transistor With a Dual-Gate for Liquid Crystal Displays

Cited by 17 publications

References 11 publications

Capacitor Reused Gate Driver for Compact In-Cell Touch Displays

Capacitor Reused Gate Driver for Compact In-Cell Touch Displays

Stability Behavior of Self-Aligned Coplanar a-IGZO Thin Film Transistors Fabricated by Deep Ultraviolet Irradiation

A-Si TFT Integrated Gate Driver Workable at −40°C Using Bootstrapped Carry Signal

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