2010
DOI: 10.1007/978-3-642-12368-9_4
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A Smart Card Implementation of the McEliece PKC

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Cited by 18 publications
(16 citation statements)
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“…S t r e n z k e in [60] describes an implementation of MECS on a smart card with an Infineon SLE 76 chip. Strenzke tested two instances of MECS based on irreducible Goppa codes with systematic public key: m = 10, n = 1024, t = 40 errors (62-bit security, 93kB key structures), and m = 11, n = 2048, t = 50 (102-bit security, 257 kB key structures).…”
Section: Mecs On Embedded and Hardware Platformmentioning
confidence: 99%
“…S t r e n z k e in [60] describes an implementation of MECS on a smart card with an Infineon SLE 76 chip. Strenzke tested two instances of MECS based on irreducible Goppa codes with systematic public key: m = 10, n = 1024, t = 40 errors (62-bit security, 93kB key structures), and m = 11, n = 2048, t = 50 (102-bit security, 257 kB key structures).…”
Section: Mecs On Embedded and Hardware Platformmentioning
confidence: 99%
“…The first truly practical scheme using error-correcting codes is due to J. Stern [101]. The scheme uses a fixed binary (k, n) parity check matrix H which is common to all users.…”
Section: Stern's Schemementioning
confidence: 99%
“…The second part of this work shows a solution for the McEliece private key, which in previously published implementations [21,18,19,22] of the McEliece PKC features the parity check matrix, the size of which is similar to that of the McEliece public key. The benefit of the parity check matrix, which is not an essential part of the private key, but a precomputation that allows faster computation of the so called syndrome vector.…”
Section: Introductionmentioning
confidence: 99%
“…Specifically, the public keys will be at least 100 KB large for reasonable security parameters, as we will see in Section 2.2. For instance, the works [18,19,20] all describe implementations of code-based encryption schemes on embedded devices, where the public key is stored in the devices NVM. The drawbacks of storing such an amount of data in the device's NVM are first of all the cost of keeping such a large amount of memory available for this purpose and also the much slower writing speed compared to RAM access.…”
Section: Introductionmentioning
confidence: 99%