A smart sampling algorithm to minimize risk dynamically

Dauzère‐Pérès, Stéphane; Rouveyrol, Jean-Loup; Yugma, Claude; Vialletelle, Philippe

doi:10.1109/asmc.2010.5551470

Cited by 37 publications

(23 citation statements)

References 9 publications

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“…Dauzère-pérès et al [67] present a sampling, scheduling, and skipping algorithm to minimize risk dynamically. The algorithm is based on a Global Sampling Indicator (GSI) that gives a weight to each lot arriving at the measurement step i.e.…”

Section: Dynamic Samplingmentioning

confidence: 99%

“…The objective is to measure the lot that brings as much information as possible on both risk reduction and process variation. In high-mix semiconductor plants, where more than 200 products can be run concurrently, dynamic sampling tech- [58] 2007 * * Holfeld et al [59] 2007 * * Good and Purdy [60] 2007 * * * Purdy et al [61] 2007 * * Kaga et al [62] 2008 * * * Jansen et al [63] 2008 * * * Hyung [64] 2008 * * Sun et al [65] 2008 * Lin et al [66] 2010 * Dauzère-pérès et al [67] 2010 * * niques are seen as more suitable. [61] and a patent can be found in [68].…”

Section: Dynamic Samplingmentioning

confidence: 99%

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A Literature Review on Sampling Techniques in Semiconductor Manufacturing

Nduhura-Munga

Rodriguez-Verjan

Dauzère‐Pérès

et al. 2013

IEEE Trans. Semicond. Manufact.

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This paper reviews sampling techniques for inspection in semiconductor manufacturing. We discuss the strengths and weaknesses of techniques developed in the last last 20 years for excursion monitoring (when a process or machine falls out of specifications) and control. Sampling techniques are classified into three main groups: static, adaptive, and dynamic. For each group, a classification is performed per year, approach, and industrial deployment. A comparison between the groups indicates a complementarity strongly linked to the semiconductor environment. Benefits and drawbacks of each group are discussed, showing significant improvements from static to dynamic through adaptive sampling techniques. Dynamic sampling seems to be more appropriate for modern semiconductor plants.

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Section: Dynamic Samplingmentioning

confidence: 99%

Section: Dynamic Samplingmentioning

confidence: 99%

A Literature Review on Sampling Techniques in Semiconductor Manufacturing

Nduhura-Munga

Rodriguez-Verjan

Dauzère‐Pérès

et al. 2013

IEEE Trans. Semicond. Manufact.

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“…The aim of the test is to quantify the limits on potential performance gains with these dynamic sampling rules with respect to the prediction capability of the trained VM model. The values of SA-NMSE defined in (10)(11) are plotted against various sampling rates and the performance of these four dynamic sampling rules are compared according to the simulated sampling capability diagram.…”

Section: A Vm For Etch Rate Using Oes Data and Gprmentioning

confidence: 99%

“…The MILP approach proposed in [8] transforms the selection of wafer sampling into a mixed-integer linear program that minimizes the sum of the individual penalties assigned for each selection rule. Other dynamic sampling algorithms are also studied in the literature, for example, the scoring algorithm in [9] for optimal wafer sampling with maximum coverage and the sampling, scheduling and skipping algorithm in [10] for minimizing risk dynamically. A fab-wide dynamic sampling application is reported in [11] that seeks to optimally balance metrology requirements, processing and risk minimization with available metrology capacity and lot-cycletime.…”

Section: Introductionmentioning

confidence: 99%

A dynamic sampling methodology for plasma etch processes using Gaussian process regression

Wan

Honari

McLoone

2013

2013 XXIV International Conference on Information, Communication and Automation Technologies (ICAT)

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Plasma etch is a key process in modern semiconductor manufacturing facilities as it offers process simplification and yet greater dimensional tolerances compared to wet chemical etch technology. The main challenge of operating plasma etchers is to maintain a consistent etch rate spatially and temporally for a given wafer and for successive wafers processed in the same etch tool. Etch rate measurements require expensive metrology steps and therefore in general only limited sampling is performed. Furthermore, the results of measurements are not accessible in real-time, limiting the options for run-to-run control. This paper investigates a Virtual Metrology (VM) enabled Dynamic Sampling (DS) methodology as an alternative paradigm for balancing the need to reduce costly metrology with the need to measure more frequently and in a timely fashion to enable waferto-wafer control. Using a Gaussian Process Regression (GPR) VM model for etch rate estimation of a plasma etch process, the proposed dynamic sampling methodology is demonstrated and evaluated for a number of different predictive dynamic sampling rules.

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“…Recently, Dauzère-Pérès et al (2010) proposed a sampling indicator to choose, in real time, which lot has to be measured. Their sampling heuristic is based on a sum of the ratios between the number of wafers processed and some associated target limits for processing machines.…”

Section: Introductionmentioning

confidence: 99%

Simulation-based optimization of sampling plans to reduce inspections while mastering the risk exposure in semiconductor manufacturing

Sahnoun¹,

Bettayeb

Bassetto

et al. 2014

J Intell Manuf

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Semiconductor manufacturing processes are very long and complex, needing several hundreds of individual steps to produce the final product (chip). In this context, the early detection of process excursions or product defects is very important to avoid massive potential losses. Metrology is thus a key step in the fabrication line. Whereas a 100 % inspection rate would be ideal in theory, the cost of the metrology devices and cycle time losses due to these measurements would completely inhibit such an approach. On another hand, the skipping of some measurements is risky for quality assurance and processing machine reliability. The purpose is to define an optimized quality control plan that reduces the required capacity of control while maintaining enough trust in quality controls. The method adopted by this research is to employ a multi-objective genetic algorithm to define the optimized control plan able to reduce the used metrology capacity without increasing risk level. Early results based on one month of real historical data computation reveal a possible reallocation of controls with a decrease by more than 15 % of metrology capacity while also reducing the risk level on the processing machine (expressed by the wafer at risk (W@R)) by 30 %.

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A smart sampling algorithm to minimize risk dynamically

Cited by 37 publications

References 9 publications

A Literature Review on Sampling Techniques in Semiconductor Manufacturing

A Literature Review on Sampling Techniques in Semiconductor Manufacturing

A dynamic sampling methodology for plasma etch processes using Gaussian process regression

Simulation-based optimization of sampling plans to reduce inspections while mastering the risk exposure in semiconductor manufacturing

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