A SMT-based diagnostic test generation method for combinational circuits

Prabhu, Sarvesh; Hsiao, Michael S.; Lingappan, Loganathan; Gangaram, Vijay

doi:10.1109/vts.2012.6231105

Cited by 17 publications

(3 citation statements)

References 12 publications

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“…Diagnostic tests are generated by a diagnostic test generation procedure [22][23][24][25][26][27][28][29][30][31][32][33][34][35]. The goal of diagnostic test generation is to distinguish pairs of faults.…”

Section: Introductionmentioning

confidence: 99%

Improving the accuracy of defect diagnosis by adding and removing tests

Pomeranz

2016

IET Computers & Digital Techniques

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An augmented defect diagnosis procedure removes tests from consideration in order to improve the accuracy of defect diagnosis by reducing the number of candidate faults. This work studies the role of diagnostic test generation in this context. Diagnostic test generation increases the number of tests that are used for defect diagnosis in order to increase its accuracy. The combined effect of using diagnostic test generation and the augmented defect diagnosis procedure is to add and remove tests in order to improve the accuracy of diagnosis. This study suggests a flow for a two-phase defect diagnosis process that combines the two procedures. Some of the issues that arise, and are addressed by this study, are: (i) which faults to target during diagnostic test generation, (ii) how to restart the augmented defect diagnosis procedure after diagnostic test generation, and (iii) how many of the diagnostic tests the augmented defect diagnosis procedure will remove.

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Section: Introductionmentioning

confidence: 99%

Improving the accuracy of defect diagnosis by adding and removing tests

Pomeranz

2016

IET Computers & Digital Techniques

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“…Production tests use fault detection tests and hence may have limited diagnosis resolution. To improve diagnosis resolution of tests used one can use diagnostic ATPGs [15]- [26] to generate test 978-1·4799-7597-6/15/$31.00 ©2015 IEEE sets to distinguish all pairs of distinguishable faults in one or more fault models. The sizes of such test sets tend to be considerably larger compared to fault detection test sets used as production tests.…”

Section: Introductionmentioning

confidence: 99%

Improving diagnosis resolution of a fault detection test set

Riefert

Sauer

Reddy

et al. 2015

2015 IEEE 33rd VLSI Test Symposium (VTS)

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Manufactured VLSI circuits using a new technology typically suffer from systematic defects that are process-dependent and at sub-nanometer feature sizes such defects may be even design-dependent. The root causes for systematic defects must be determined to ramp up yields. Volume diagnosis is becoming popular to identify root causes for systematic defects. Volume diagnosis uses logic diagnosis based on failing circuit responses to production tests of a large number of fail ing devices, followed by statistical analysis methods to determine the root cause (s) for yield limiters. Typically production tests use fault detection tests and hence may have limited diagnosis resolution. To improve diagnosis resolution diagnostic ATPGs can be used to generate test sets to distinguish all pairs of distinguishable faults in one or more fault models. The sizes of such tests tend to be considerably higher than fault detection test sets used as production tests. For this reason, generation of test sets that detect faults and also possess a high diagnosis resolution is important.In this work we present a method to improve the diagnosis resolution of a compact fault detection test set without increasing pattern count or decreasing fault coverage. The basic idea of the approach is to generate a SAT formula which enforces diagnosis and is solved by a MAX-SAT solver which is a SAT-based maximization tool. We believe this is the first time a method to improve diagnosis resolution of a test set of given size has been reported. Experimental results on ISCAS 89 circuits demonstrate the effectiveness of the proposed method.

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“…In [4] stuck-at fault ATPG is used to generate test vector that distinguishes two faults by modifying the original circuit and inserting multiplexers at places where faults are present. [5] is a variation of [4] where Satisfiability Modulo Theory(SMT) is used to target multiple fault pairs in single iteration. Here corresponding to each gate there is a n-bit vector (n being the number of faults) which stores the response due to each fault.…”

Section: Introductionmentioning

confidence: 99%

Don't Care Filling for Better Diagnostic Test Set

Bhar

Chattopadhyay

Sengupta

et al. 2013

2013 International Conference on Communication Systems and Network Technologies

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Before delivering, the manufactured ICs are tested for defects. Diagnosis is the procedure to determine the sites where defects are likely to be present in a chip that failed a test set. For any diagnosis algorithm the accuracy of diagnosis depends on the test pattern set employed. More the test pattern set distinguishes fault pairs, more is the diagnosis quality. This paper addresses issue of assigning values to don't care bits (X bits) in the test pattern set so that the circuit can be reasonably diagnosed by analyzing the output response. For this, a Particle Swarm Optimization (PSO) based approach has been proposed to fill the don't-care bits. The proposed algorithm when run on full-scan ISCAS'89 benchmark circuits shows significant improvement over 0-fill and 1-fill based don't care filling and reasonably good improvement over random-fill based techniques.

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A SMT-based diagnostic test generation method for combinational circuits

Cited by 17 publications

References 12 publications

Improving the accuracy of defect diagnosis by adding and removing tests

Improving the accuracy of defect diagnosis by adding and removing tests

Improving diagnosis resolution of a fault detection test set

Don't Care Filling for Better Diagnostic Test Set

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