A software approach for combating asymmetries of non-volatile memories

Li, Yong; Chen, Yiran; Jones, Alex K.

doi:10.1145/2333660.2333708

Cited by 42 publications

(21 citation statements)

References 11 publications

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“…Ferreira et al [33] present write minimization, unnecessary writes reduction, and a wear-leveling scheme to increase the lifetime of PCM-based main memory. Software dispatch [34] distributes data to different memories depending on data access characteristics. Besides, In [35], Dong et al study the endurance variation of PCM cells, and propose a variant of wear leveling mechanism, through physical address re-mapping and data swapping, to balance wear rates of PCM cells across the whole PCM chip.…”

Section: Related Workmentioning

confidence: 99%

Energy-aware assignment and scheduling for hybrid main memory in embedded systems

Wang

Guan

et al. 2015

Computing

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In embedded systems, especially battery-driven mobile devices, energy is one of the most critical performance metrics. Due to its high density and low standby power, phase change memory (PCM), an emerging non-volatile memory device, is becoming a promising dynamic random access memory (DRAM) alternative. Recent studies have proposed the hybrid main memory architecture integrating both PCM and DRAM to fully take advantage of the properties of both memories. However, the low power performance of PCM in the hybrid main memory architecture has not been fully explored. Therefore, it becomes an interesting problem to utilize PCM and DRAM as hybrid main memory for energy optimization in embedded systems. In this paper, we present an energy optimization technique for hybrid main memory architecture. The objective is to fully utilize PCM to reduce the energy consumption while ensuring that the real-time performance of applications are guaranteed. We propose a two-phase approach to solve hybrid main memory address mapping problem. In the first phase, we calculate energy and time cost for each address based on the task models. Then the applications can be modeled as data-flow graph nodes, and different access times will associate with different energy consumption. In the second phase, for different memory types and the given timing constraint, we formulate the scheduling problem as an integer linear programming (ILP) model and obtain an optimal solution. The 123 G. Wang et al.ILP model can map a proper memory type for each address such that the total energy consumption can be minimized while the timing constraint is satisfied. In addition, we propose a heuristic approach to efficiently obtain a near-optimal solution. We conduct experiments on an ARM-based simulator. The experimental results show that our method can effectively reduce the energy consumption with the least system cost compared with the previous work.

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Section: Related Workmentioning

confidence: 99%

Energy-aware assignment and scheduling for hybrid main memory in embedded systems

Wang

Guan

et al. 2015

Computing

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“…But the target of this technique is a pure STT-RAM cache, so it can not be applied directly to hybrid caches. A lot of researches [3,9,8,14,18,17] utilize a migration technique for adapting block placements, but in our proposed partitioning technique, a conventional migration scheme [17] can reduce the energy efficiency of hybrid caches by breaking the partitioning decision.…”

Section: Reducing Write Overhead Of Stt-rammentioning

confidence: 99%

“…Such characteristics can significantly increase energy consumption and degrade performance of the system if the program running on the processor cores need frequent writes into the shared cache. To mitigate the adverse effect of the characteristics of STT-RAM, many methods are proposed [1,3,7,9,18,17] on hybrid caches, where a small SRAM cache is combined with a large STT-RAM cache. In the hybrid caches, a block that is expected to be written frequently is placed in the SRAM cache, which has much lower write overhead compared to STT-RAM.…”

Section: Introductionmentioning

confidence: 99%

Energy-Efficient Partitioning of Hybrid Caches in Multi-core Architecture

Lee

Choi

2015

VLSI-SoC: Internet of Things Foundations

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International audienceThis chapter presents a technique for reducing energy consumed by hybrid caches that have both SRAM and STT-RAM (Spin-Transfer Torque RAM) in multi-core architecture. It is based on dynamic way partitioning of the SRAM cache as well as the STT-RAM cache. Each core is allocated with a specific number of ways consisting of SRAM ways and STT-RAM ways. Then a cache miss fills the corresponding block in the SRAM or STT-RAM region based on an existing technique called read-write aware region-based hybrid cache architecture. Thus, when a store operation from a core causes an L2 cache miss (store miss), the block is assigned to the SRAM cache. When a load operation from a core causes an L2 cache miss (load miss) and thus causes a block fill, the block is assigned to the STT-RAM cache. However, if all the allocated ways are already placed in the SRAM, then the block fill is done into the SRAM regardless of store or load miss. The partitioning decision is updated periodically. We further improve our technique by adopting the so called allocation switching technique to avoid too much unbalanced use of SRAM or STT-RAM. Simulation results show that the proposed technique improves the performance of the multi-core architecture and significantly reduces energy consumption in the hybrid caches compared to the state-of-the-art migration-based hybrid cache management

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“…There is a large amount of research work on NVM based systems [10,16,25,28,36]. In general, these work can be categorized into three types, which are physic material [10,28,34], lifespan issues [4,12,20,26] and energy consumption saving [5,18,19,27,30,35].…”

Section: Related Workmentioning

confidence: 99%

A content-aware writing mechanism for reducing energy on non-volatile memory based embedded storage systems

Zhuge

Liu

et al. 2013

Des Autom Embed Syst

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Emerging byte-addressable non-volatile memory (NVM), such as phase change memory has many advantages in terms of low power consumption, high density, in-place update, and higher write endurance. Reducing the energy consumption of NVM is a fundamental issue when the technology is considered as an alternative to secondary storage in embedded systems. In the design of energy efficiency approaches, one of the most challenging problems is to reduce unnecessary write activities on NVM. In this paper, we present an optimal content-aware NVM memory writing mechanism, CA-NVM, to effectively select a free NVM page for each write request from file system to reduce write activities, since write activities account for most of energy consumption in NVM storage. In order to speed up the procedure of selecting a free page, we introduce a sampling mechanism, by which we only pick a few bits from the free page and the logical page to be written for comparison. Those sample bits of free pages are stored in a special area such that they can be indexed quickly. We conduct a series of experiments based on realistic traces, and the experimental results show that the proposed technique can reduce write activities up to 36.03 %, and reduce energy consumption by 21.3 % on average compared with a random based free-page allocation mechanism.

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A software approach for combating asymmetries of non-volatile memories

Cited by 42 publications

References 11 publications

Energy-aware assignment and scheduling for hybrid main memory in embedded systems

Energy-aware assignment and scheduling for hybrid main memory in embedded systems

Energy-Efficient Partitioning of Hybrid Caches in Multi-core Architecture

A content-aware writing mechanism for reducing energy on non-volatile memory based embedded storage systems

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