A software PAM4 clock data recovery algorithm for high‐speed serial communication

Abstract

Time jitter analysis is an important means to evaluate the performance of a high‐speed serial communication system. Clock data recovery (CDR) is a critical component of a high‐speed serial link that recovers the reference clock from a signal for jitter analysis. Traditional studies focused on CDR technology for the non‐return‐to‐zero pattern based on a hardware design, but little work has been devoted to the software CDR especially for the four‐level pulse amplitude modulated (PAM4) encoded data signals. This study proposes a new software algorithm to recover clocks from PAM4 signals that is capable of extracting synchronous clocks from PAM4 signals to design an ideal software phase‐locked loop for clock recovery. The proposed algorithm extracts more types of data transition edges than hardware methods to avoid the loss of jitter information. Besides, the algorithm designs an ideal phase‐locked loop to improve the filtering accuracy. This algorithm has been implemented in MATLAB, and shows superior performance to that of conventional CDR technology.