A software performance simulation methodology for rapid system architecture exploration

Kirchsteiger, Christoph M.; Schweitzer, H.; Trummer, Christoph; Steger, Christian; Weiß, Reinhold; Pistauer, Markus

doi:10.1109/icecs.2008.4674898

Cited by 8 publications

(3 citation statements)

References 8 publications

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“…SyAD R provides the development of entire HW/SW system models and supports a multilanguage and multi-level co-simulation framework of Sys-temC, MATLAB Simulink, VHDL and VHDL-AMS. In our previous work [10] we evaluated the accuracy of our generated SystemC model by comparing it with the Sim-pleScalar/ARM performance ISS [4]. Fig.…”

Section: Resultsmentioning

confidence: 99%

Rapid exploration of multimedia system-on-chips with automatically generated software performance models

Kirchsteiger

Schweitzer

Trummer

et al. 2008

2008 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia

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A challenge in the design space exploration of todays' multimedia system-on-chip (SoC) designs is to rapidly evaluate the large number of different processor types. This limitation is resolved by our methodology, originated from the SIMBA 1 project. It automatically generates a Sys-temC performance model of the software code with respect to the chosen processor type. The generated performance model consists of the original software C-code annotated with SystemC wait statements to consider the execution time on the target processor. These wait statements are automatically determined by the target cross-compiler's assembler code and the processor datasheet and consider also memory accesses and pipeline effects. In our experiments we automatically generate both a performance model of an ARM and a TI processor. This only requires the target cross-compiler and the processor datasheet and is widely applicable to various processor types. We show that our models can be used easily to compare the software performance on these platforms. We also demonstrate that the models can be smoothly integrated into an existing multimedia SoC for a rapid software-driven architecture exploration.978-1-4244-2612-6/08/$25.00

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Section: Resultsmentioning

confidence: 99%

Rapid exploration of multimedia system-on-chips with automatically generated software performance models

Kirchsteiger

Schweitzer

Trummer

et al. 2008

2008 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia

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“…One method to speed up simulation consists in associating a temporal dimension with an event. An automatic delay-annotated mechanism to replace the use of Instruction-Set-Simulation (ISS) in SystemC simulations is presented in [21]. The contributions presented in [22], are based on packet latency estimations to replace detailed Network-on-Chip models in full-system performance simulators.…”

Section: Input Datamentioning

confidence: 99%

A combined fast/cycle accurate simulation tool for reconfigurable accelerator evaluation: application to distributed data management

Lenormand

Goubier

Cudennec

et al. 2020

2020 International Workshop on Rapid System Prototyping (RSP)

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Parallel computing systems based on reconfigurable accelerators are becoming (1) increasingly heterogeneous, (2) difficult to design and (3) complex to model. Such modeling of a parallel computing system helps to evaluate its performance and to improve its architecture before prototyping. This paper presents a simulation tool aiming to study the integration of reconfigurable accelerators in scalable distributed systems and runtimes, such as S-DSM systems, where S-DSM (softwaredistributed shared memory) is a paradigm to ease data management among distributed nodes. This tool allows us to simulate the execution of irregular compute kernels accessing distributed data. To deal with the complexity of modeling (3) the complete system we used a hybrid methodology. We integrated the simulation engine into the S-DSM. The distributed data management part is executed on the physical architecture allowing to generate precise and faithful latencies, and the accelerator simulation is cycle accurate. We used general sparse matrix-matrix multiplication (SpGEMM) as a case study. We show that the use of this tool makes it possible to analyze the behavior of an heterogeneous system (1) with rapid prototyping and simulation. The analysis of the results allowed to determine the correct sizing of the architecture (2) to obtain the best performance. The tool allowed to identify the bottleneck of our architecture and confirmed the possibility of hiding data access latencies. Our simulation platform allows to emulate a heterogeneous distributed system by introducing a slowdown between 1.2 and 3.7 times compared to the compute kernel simulation alone.

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“…Several estimation and annotation techniques have been developed to model SW at in native co-simulation [6][7][8][9][10]. Even commercial tools have been developed to automatically estimate and annotate the SW code [11].…”

Section: Related Workmentioning

confidence: 99%

Automatic HW/SW Interface Modeling for Scratch-Pad and Memory Mapped HW Components in Native Source-Code Co-simulation

Posadas

Villar

2009

IFIP Advances in Information and Communication Technology

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Abstract. Native execution of instrumented code is commonly used for early, high-level SW simulations. SW code developed for a target platform is executed in a host computer for fast functional verification and performance estimations. However, as the native platform is different than the target platform, directly writing the peripheral registers or handling scratch pad memories makes the native execution to crash. Previous works require manual recoding to solve this problem. This paper presents a library that automatically solves the problem of simulating directly, fixed memory accesses. HW accesses are detected at run-time in the native execution and redirected to a target platform model. Thus, native HW/SW co-simulation is performed without any recoding effort. Both peripherals only requiring data transfers and peripherals also requiring communication event delivery are automatically managed.

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A software performance simulation methodology for rapid system architecture exploration

Cited by 8 publications

References 8 publications

Rapid exploration of multimedia system-on-chips with automatically generated software performance models

Rapid exploration of multimedia system-on-chips with automatically generated software performance models

A combined fast/cycle accurate simulation tool for reconfigurable accelerator evaluation: application to distributed data management

Automatic HW/SW Interface Modeling for Scratch-Pad and Memory Mapped HW Components in Native Source-Code Co-simulation

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