A Solution of the All-Pairs Shortest Paths Problem on the Cell Broadband Engine Processor

Matsumoto, Kazuya; Sedukhin, Stanislav G.

doi:10.1587/transinf.e92.d.1225

Cited by 9 publications

(6 citation statements)

References 17 publications

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“…The importance of efficient processing of the APSP problem has led to a substantial amount of previous work that deals with the design and optimisation of APSP either for commodity processors [6,7,8], or for dedicated hardware [9,10,11,12]. Matsumoto et al [6] proposed a CPU-GPU hybrid system that is reported to have outperformed previous work on APSP for commodity processors.…”

Section: Related Workmentioning

confidence: 99%

“…Because of the small-world phenomenon the number of vertices in each BFS level grows very rapidly, leading to most edges being examined in one or two BFS levels, the critical BFS levels. Algorithm 4 describes the bottom-up algorithm that replaces lines (6)(7)(8)(9)(10)(11)(12)(13)(14)(15)(16)(17)(18)(19)(20)(21)(22)(23)(24) in Algorithm 3, i.e. steps 1-4.…”

Section: Hybrid Bfs Kernelmentioning

confidence: 99%

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Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study

Betkaoui

Wang

Thomas

et al. 2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

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This paper proposes a highly parallel and scalable reconfigurable design for the All-Pairs Shortest-Paths (APSP) algorithm for very sparse networks. Our work is motivated by a computationally intensive bioinformatics application that employs this memory-latency bound algorithm. The proposed design methodology takes advantage of distributed on-chip memory resources of modern FPGAs to reduce accesses to high-latency off-chip memories. We develop design optimisations that yield different FPGA configurations which are selected at run time based on the input graph data. Using human brain network data, we are able to achieve performance results superior to those from multi-core CPU and GPU, while attaining linear scaling over the number of processors introduced. Our FPGA-based APSP design is over 10 times faster than a quad-core CPU implementation and 2-5 times faster than an AMD Cypress GPU implementation.

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Section: Related Workmentioning

confidence: 99%

Section: Hybrid Bfs Kernelmentioning

confidence: 99%

Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study

Betkaoui

Wang

Thomas

et al. 2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

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“…On the other hand, in [12], they focus on solving the shortest paths problems for all pairs of nodes, where the advantages of using the CBE are demonstrated. As such, this research focuses on computing the Kleene star of the weighted adjacency matrix of a DAG type, and an implementation of this using SIMD instructions [13] and multiple cores in parallel [14], both of which are available on the CBE, is carried out.…”

Section: Introductionmentioning

confidence: 99%

High-Speed Computation of the Kleene Star in Max-Plus Algebraic System Using a Cell Broadband Engine

Goto

2010

IEICE Trans. Inf. & Syst.

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SUMMARYThis research addresses a high-speed computation method for the Kleene star of the weighted adjacency matrix in a max-plus algebraic system. We focus on systems whose precedence constraints are represented by a directed acyclic graph and implement it on a Cell Broadband Engine TM (CBE) processor. Since the resulting matrix gives the longest travel times between two adjacent nodes, it is often utilized in scheduling problem solvers for a class of discrete event systems. This research, in particular, attempts to achieve a speedup by using two approaches: parallelization and SIMDization (Single Instruction, Multiple Data), both of which can be accomplished by a CBE processor. The former refers to a parallel computation using multiple cores, while the latter is a method whereby multiple elements are computed by a single instruction. Using the implementation on a Sony PlayStation 3 TM equipped with a CBE processor, we found that the SIMDization is effective regardless of the system's size and the number of processor cores used. We also found that the scalability of using multiple cores is remarkable especially for systems with a large number of nodes. In a numerical experiment where the number of nodes is 2000, we achieved a speedup of 20 times compared with the method without the above techniques. key words: directed acyclic graph, max-plus algebra, scheduling, parallel processing, vector processing, Cell Broadband Engine IntroductionThis research aims to develop a fast computation method for the representation matrix in a state-space representation in max-plus algebra [1], [2]. This approach is often used in solvers for a class of scheduling problems. Specifically, we focus on quickly calculating the transition matrix, which requires a high computation load using this approach. For the computation, we use a processor called the Cell Broadband Engine (CBE) [3]-[6], which has instructions for vector operations and parallel processing.The features of the class of focused systems are: (1) parallel execution of multiple tasks, (2) synchronization of multiple tasks, and (3) no-concurrency between the previous or succeeding job. Such systems can also be explained as repetitive discrete event systems in which a number of jobs are processed sequentially using the same facilities in FIFO order. We assume that the precedence relationships of the system are described by a Directed Acyclic Graph (DAG). The behavior of this class can be represented by a pair of simple equations in max-plus algebra, called the state-space representation. Since this is similar to the representation in modern control theory, a number of research developments Manuscript received October 30, 2009. Manuscript revised January 29, 2010. † The author is with Nagaoka University of Technology, Nagaoka-shi, 940-2188 Japan.a) E-mail: hgoto@kjs.nagaokaut.ac.jp DOI: 10.1587/transinf.E93. D.1798 in modern control theory have been applied to various kinds of scheduling problems [7]- [9]. The state-space representation consists of a pair of state ...

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“…Some attempts to implement the transitive closure on the CELL can be found in the literature. Among them, we point out the works described in [5] (up to 50 GFLOPS) and in [8] (up to 78 GFLOPS in perspective). The two solutions are both based on a block partitioning of the basic Warshall-Floyd procedure together with ad-hoc memory optimization and efficient global synchronization.…”

Section: Introductionmentioning

confidence: 99%

Ring Pipelined Algorithm for the Algebraic Path Problem on the CELL Broadband Engine

Tadonki

2010

2010 22nd International Symposium on Computer Architecture and High Performance Computing Workshops

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Print ISBN: 978-1-4244-8877-3International audienceThe algebraic path problem (APP) unifies a number of related combinatorial or numerical problems into one that can be resolved by a generic algorithmic schema. In this paper, we propose a linear SPMD model based on the Warshall-Floyd procedure coupled with a systematic shift-toroïdal. Our scheduling requires a number of processors that equals the size of the input matrix. With a fewer number of processors, we exploit the modularity revealed by our linear array to achieve the task using a locally parallel and globally sequential} (LPGS) partitioning. Whatever the case, we just need each processor to have a local memory large enough to house one (probably block) column of the matrix. Considering these two characteristics clearly justify an implementation on the CELL Broadband engine, because of the efficient SPE to SPE communication bandwidth and the absolute power of each SPE. We report our experimentations on a QS22 CELL blade on various input configurations and exhibit the efficiency and scalability of our implementation. We show that, with a highly optimized Warshall-Floyd kernel, we could get close to 80 GFLOPS in simple precision with 8 SPEs which represents 80% of the peak performance for the APP on the CELL

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A Solution of the All-Pairs Shortest Paths Problem on the Cell Broadband Engine Processor

Cited by 9 publications

References 17 publications

Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study

Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study

High-Speed Computation of the Kleene Star in Max-Plus Algebraic System Using a Cell Broadband Engine

Ring Pipelined Algorithm for the Algebraic Path Problem on the CELL Broadband Engine

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