A space-efficient flash translation layer for CompactFlash systems

Abstract

Abstract-Flash memory is becoming increasingly important as nonvolatile storage for mobile consumer electronics due to its low power consumption and shock resistance. However, it imposes technical challenges in that a write should be preceded by an erase operation, and that this erase operation can be performed only in a unit much larger than the write unit. To address these technical hurdles, an intermediate software layer called a flash translation layer (FTL) is generally employed to redirect logical addresses from the host system to physical addresses in flash memory. Previous approaches have performed this address translation at the granularity of either a write unit (page) or an erase unit (block). In this paper, we propose a novel FTL design that combines the two different granularities in address translation. This is motivated by the idea that coarse grain address translation lowers resources required to maintain translation information, which is crucial in mobile consumer products for cost and power consumption reasons, while fine grain address translation is efficient in handling small size writes. Performance evaluation based on trace-driven simulation shows that the proposed scheme significantly outperforms previously proposed approaches.

ICAP, a new flash wear-leveling algorithm inspired by locality

“…NFTL can use less RAM to manage larger flash drive. [12][13][14][15] combine the advantages of FTL and NFTL by using hybrid methods.…”

Exploit real-time fine-grained access patterns to partition write buffer to improve SSD performance and life-span

“…It was inspired by virtual memory systems, and will load a fragment of the page mapping table into RAM on demand. Most real-world systems use log-structured block-based mapping schemes [10]- [12], which are hybrid mapping schemes inspired by log-based file systems [13]. In these systems, regular data are still mapped in the block granularity to reduce the space overhead, while any updated pages will be temporarily appended into special log blocks which are mapped in the unit of a page.…”

“…In this work, we assume that our SSD system uses a log-structured block-based mapping FTL. In our simulation, we implemented the FTL proposed by Jesung et al in [10] (a.k.a. BAST) .…”

“…It implements the LRU buffer cache including the baseline heuristic write buffer (similar to the scheme proposed in CFLRU) as well as our pattern detector and pattern-based flushing scheme. A log-structured block-based FTL [10] is implemented in the SSD simulator. The system starts to write dirty pages back to the SSD if the total number of dirty pages exceeds an upper bound (20% of total buffer capacity in the experiments).…”

Clustering data according to update frequency to reduce garbage-collection overhead in solid-state drives

“…Thus, the location of valid data changes on every write request; the FTL tracks the current location of each logical address with a mapping table. According to the mapping granularity between a logical address and its physical address, the FTL is classified as page mapping [1,2,3], block mapping [4], and hybrid mapping [5,6,7,8]. The pagemapping FTL uses NAND pages as a mapping unit and delivers better performance than the other schemes.…”