A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array−Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

doi:10.3390/s17071493

Cited by 30 publications

(38 citation statements)

References 33 publications

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“…Since the system we designed is a two-channel stripmap SAR imaging system, the inverse-filter method is executed to complete data preprocessing which consumes more time than that of stripmap SAR imaging system. Taking into account the data granularity and the complexity of the algorithm, the processing time of reference [12] is comparable to ours. And the resource utilization of our design is acceptable.…”

Section: Resultsmentioning

confidence: 77%

“…Compared with [13,14], taking into account the data granularity processed, the proposed system shows advantages in processing time. Reference [12] describes a stripmap SAR system and it takes 12.1 s to process stripmap SAR raw data with a granularity of 16384×16384. Since the system we designed is a two-channel stripmap SAR imaging system, the inverse-filter method is executed to complete data preprocessing which consumes more time than that of stripmap SAR imaging system.…”

Section: Resultsmentioning

confidence: 99%

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Design and implementation of a multi-channel space-borne SAR imaging system on Vivado HLS

Gao

Yang

Xie

et al. 2018

IEICE Electron. Express

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New generation space-borne SAR (synthetic aperture radar) systems require high real-time processing performance and have size, weight and power constrains. This paper presents a multi-channel stripmap SAR imaging system implemented on an FPGA platform. In order to reduce FPGA design cost, a high-level synthesis tool Xilinx Vivado HLS is applied to design and implement the SAR imaging system. FFT algorithms in the imaging algorithm use FFT IP cores in FPGA, and the rest is customized on HLS. The modules designed on HLS are optimized and packaged as IP blocks for FPGA implementation of the imaging system. The performance and resource utilization of the whole system are evaluated by processing a two-channel SAR raw data with a granularity of 16384×4096. The system can complete imaging in about 4.7 s at 100MHz operating frequency.

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Section: Resultsmentioning

confidence: 77%

Section: Resultsmentioning

confidence: 99%

Design and implementation of a multi-channel space-borne SAR imaging system on Vivado HLS

Gao

Yang

Xie

et al. 2018

IEICE Electron. Express

Self Cite

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“…The architecture proposed of the hardware used to implement the LST algorithm (see Figure 1), in our implementation we have devices our algorithm in two parts (see equations (2) and equations (3)):…”

Section: Proposed Hardware Fpga Architecture For the Lst-sw Algorithmmentioning

confidence: 99%

“…With their continuous development and improvement, remote sensing satellites [1] are increasingly being utilized and use of the latest available technological components. The emergence of peripherals such as Field Programmable Gate Arrays (FPGAs) [2], which can bridge the gap in on-board and real-time analysis of remote sensing data. Some FPGAs incorporate a large number of arithmetic blocks that can be low-complexity blocks such as simple multipliers or can be relatively more complex like the Digital Signal Processing (DSP) units which consist of combinations of various components like multipliers, adders, accumulators, shift registers.…”

Section: Introductionmentioning

confidence: 99%

An approch for FPGA implementation of LST-SW algorithm

Makhloufi¹,

Adib²,

Raissouni³

2019

Proceedings of the Third International Conference on Computing and Wireless Communication Systems, ICCWCS 2019, April 24-25, 20

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Satellite remote sensing (SRS) needs to make use of up-to-date technology. The trend in SRS missions has always been towards using hardware devices with smaller size, lower cost, more flexibility, and higher computational power. Therefore, Field Programmable Gate Array (FPGA) technology is highly used by the scientific community and hardware developers to implement different SRS algorithms. Thus, FPGAs offer well-suited architectural features; large number of programmable logic elements, distributed and block RAMs, DSP and register slices and look up tables. This paper describes an approach to the implementation of the Land Surface Temperature Split-Window (LST-SW) algorithm structure based on FPGA technology.

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“…For instance, a high-efficiency system based on Zynq SoPC devices for hyperspectral image classification was presented in Reference [32]. Other on-board application scenarios have covered Synthetic Aperture RADAR (SAR) image processing [33,34] or Support Vector Machines (SVM) for cloud detection [35].…”

Section: Distributed On-board Processingmentioning

confidence: 99%

A Runtime-Scalable and Hardware-Accelerated Approach to On-Board Linear Unmixing of Hyperspectral Images

et al. 2018

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Space missions are facing disruptive innovation since the appearance of small, lightweight, and low-cost satellites (e.g., CubeSats). The use of commercial devices and their limitations in cost usually entail a decrease in available on-board computing power. To face this change, the on-board processing paradigm is advancing towards the clustering of satellites, and moving to distributed and collaborative schemes in order to maintain acceptable performance levels in complex applications such as hyperspectral image processing. In this scenario, hybrid hardware/software and reconfigurable computing have appeared as key enabling technologies, even though they increase complexity in both design and run time. In this paper, the ARTICo3 framework, which abstracts and eases the design and run-time management of hardware-accelerated systems, has been used to deploy a networked implementation of the Fast UNmixing (FUN) algorithm, which performs linear unmixing of hyperspectral images in a small cluster of reconfigurable computing devices that emulates a distributed on-board processing scenario. Algorithmic modifications have been proposed to enable data-level parallelism and foster scalability in two ways: on the one hand, in the number of accelerators per reconfigurable device; on the other hand, in the number of network nodes. Experimental results motivate the use of ARTICo3-enabled systems for on-board processing in applications traditionally addressed by high-performance on-Earth computation. Results also show that the proposed implementation may be better, for certain configurations, than an equivalent software-based solution in both performance and energy efficiency, achieving great scalability that is only limited by communication bandwidth.

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A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array−Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

Cited by 30 publications

References 33 publications

Design and implementation of a multi-channel space-borne SAR imaging system on Vivado HLS

Design and implementation of a multi-channel space-borne SAR imaging system on Vivado HLS

An approch for FPGA implementation of LST-SW algorithm

A Runtime-Scalable and Hardware-Accelerated Approach to On-Board Linear Unmixing of Hyperspectral Images

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