A spatial path scheduling algorithm for EDGE architectures

Abstract

Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed microarchitectures in which the compiler forms dataflow graphs that specify how the microarchitecture maps instructions onto a distributed execution substrate. This paper describes a compiler scheduling algorithm called spatial path scheduling that factors in previously fixed locations - called anchor points - for each placement. This algorithm extends easily to different spatial topologies. We augment this basic algorithm with three heuristics: (1) local and global ALU and network link contention modeling, (2) global critical path estimates, and (3) dependence chain path reservation. We use simulated annealing to explore possible performance improvements and to motivate the augmented heuristics and their weighting functions. We show that the spatial path scheduling algorithm augmented with these three heuristics achieves a 21% average performance improvement over the best prior algorithm and comes within an average of 5% of the annealed performance for our benchmarks.

A general constraint-centric scheduling framework for spatial architectures

“…Compared to the TRIPS SPS specialized scheduler (a cumulated multi-year effort spanning several publications [9,12,40]), our ILP scheduler performs competitively as summarized below. 3 Compared to SPS (a)Better on 22 of 43 benchmarks up to 21% GM +2.9% (b)Worse on 18 of 43 benchmarks within 4.9% GM -1.9% (typically 2%) (c)5.4%, 6.04%, and 13.2% worse on ONLY 3 benchmarks Compared to GRST Consistently better, up to 59% better; GM +30% Groups (a) and (b) show the ILP scheduler is capturing the architecture/scheduler interactions well.…”

“…For this reason, the DySER scheduler first optimizes for latency, adds the latency of the solution as a constraint, then optimizes for throughput by minimizing latency mismatch M IS, as below: min LAT s.t. [ 1,2,3,4,5,6,8,9,11,12,13,14,15,16,17,18,24] min M IS s.t. [ 1,2,3,4,5,6,8,9,11,12,13,14,15,16,17,18,24] and LAT = LAT optimal…”

“…Instead, the focus of architecture-specific schedulers has typically been on developing polynomial-time algorithms that approximate the optimal solution using knowledge about the architecture. Chronologically, this body of work includes the BUG scheduler for VLIW proposed in 1985 [17], UAS scheduler for clustered VLIW [41], synchronous data-flow graph scheduling [7], RAW scheduler [36], CARS VLIW code-generation and scheduler [33], TRIPS scheduler [12,40], Wavescalar scheduler [37], and CCA scheduler proposed in 2008 [43]. While heuristic-based approaches are popular and effective, they have three problems: i) poor compiler developer/architect productivity since new algorithms, heuristics, and implementations are required for each architecture, ii) lack of insight on optimality of solution, and iii) sandboxing of heuristics to specific architectures -understanding and using techniques developed for one spatial architecture in another is very hard.…”

“…We implement these constraints and report on results for three architectures picked to stress our ILP scheduler in various ways. To stress the performance deliverable by our general ILP approach, we consider TRIPS because it is a mature architecture with sophisticated specialized schedulers resulting from multi-year efforts [1,9,12,40]. To represent the emerging class of energy-centric specialized spatial architectures, we consider DySER [26].…”

Coarse-Grained Reconfigurable Array Architectures

“…Finally, compilation techniques have been developed that are really specialized for the TRIPS array layout and for its out-of-order execution [12].…”