A Specification Methodology by a Collection of Compact Properties as Applied to the Intel® Itanium™ Processor Bus Protocol

Abstract

Abstract. In practice, formal specifications are often considered too costly for the benefits they promise. Specifically, interface specifications such as standard bus protocol descriptions are still documented informally, and although many admit formal versions would be useful, they are dissuaded by the time and effort needed for development. We champion a formal specification methodology that attacks this costvalue problem from two angles. First, the framework allows formal specifications to be feasible for signal-level bus protocols with minimal effort, lowering costs. And second, a specification written in this style has many different uses, other than as a precise specification document, resulting in increased value over cost. This methodology allows the specification to be easily transformed into an executable checker or an simulation environment, for example. In an earlier paper, we demonstrated the methodology on a widelyused bus protocol. Now, we show that the generalized methodology can be applied to more advanced bus protocols, in particular, the Intel Itanium TM Processor bus protocol. In addition, the paper outlines how writing and checking such a specification revealed interesting issues, such as deadlock and missed data phases, during the development of the protocol.

Synthesis of Trigger Properties

“…For that reason, regular expressions have proved to be quite popular with verification engineers, 3 to the point that the regular layer is that main layer of SVA [VR05]. The key observation is that a very large fraction of temporal properties that arise in practice can be expressed in the form of e 1 →e 2 or e 1 →!e 2 (we generally use PSL syntax in this paper), which means that an e 1 pattern should, or should not, be followed by an e 2 pattern; see, for example, [SDC01]. As an example, consider the property: "If a snoop hits a modified line in the L1 cache, then the next transaction must be a snoop writeback."…”

HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms

“…Because of pipeline characterization, there exist two transfers on the bus at the same time that we must record enough information to keep checking the correctness of bus protocol. Shimizu et al [10] also used formal modeling and symbolic check to verify Intel Itanium processor bus functionality. Formal modeling and symbolic check is the one of most popular topics in this domain.…”

Strategies for mainstream usage of formal verification

“…While assertions can also be used with simulations, the styles of coding differ significantly between the assertions written for FAV as compared to the assertions written for ABS. It is necessary to write FAV-friendly assertions in monitor style [3] that are optimized for minimizing the introduction of extra state elements. In contrast, assertions and code written for ABS typically do not pay any heed for extra state elements being added, and this is the coding practice that the verification engineers are currently accustomed to.…”