A Spectral Graph Sparsification Approach to Scalable Vectorless Power Grid Integrity Verification

Zhao, Zhiqiang; Feng, Zhuo

doi:10.1145/3061639.3062193

Cited by 16 publications

(21 citation statements)

References 13 publications

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“…where u ∈ R n is a vector of artificial variables with the units of volts that is used to carry out the above maximization. Notice that if α = 0, then the constraints of the optimization problem (15) become Pu ≤ 0 and u ≥ 0; because P ≥ 0 and has exactly one 1 in each row, it follows that u = 0 is the only vector satisfying those constraints. Also, recall that for any α ∈ [0, 1], u * (α) is defined to be a vector function that evaluates to a value of u for which (15) attains its maximum.…”

Section: And It Is Easy To See That the Node Safety Conditionmentioning

confidence: 99%

“…These simulation-based techniques include [7]- [10]. An alternative power grid verification scheme, such as in [11]- [15], relies on information that may be available at an early stage of the design in the form of current budgets or current constraints. These methods are referred to as vectorless verification and consist of finding the worst case voltage fluctuations at all nodes of the grid under all possible transient current waveforms that satisfy user-specified current constraints.…”

Section: Introductionmentioning

confidence: 99%

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Power Scheduling With Active <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math> </inline-formula> Power Grids

Moudallal

Najm

2019

IEEE Trans. VLSI Syst.

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Power gating is widely used in large chip design as a way to manage the total power dissipation and avoid overheating. It works by turning OFF the power supply to circuit blocks that are not required to operate in certain operational modes. Many authors have studied the scheduling of chip workload to manage total power and temperature. But power gating also has an impact on the supply voltage levels across the die, because voltage drop is generated in the grid depending on the combination of blocks that are ON. We consider the question of how to manage the chip workload so that supply voltage variations remain within specs. The worst case voltage drop is the result of two things: the power budgets that were allocated to the various circuit blocks during the design process and the combination of blocks that are turned ON in a given operational mode. In this paper, we propose a framework to manage this tradeoff between how many blocks are ON simultaneously and how big the power budgets of the individual blocks are, assuming resistive and capacitive (RC) elements in the power grid model. Subject to user guidance, we generate block-level circuit current constraints as well as an implicit binary decision diagram (BDD) that helps identify the safe working modes. If the blocks are designed to respect these constraints, then the BDD can be used during normal operation to check whether a candidate working mode is safe or not.

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Section: And It Is Easy To See That the Node Safety Conditionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Power Scheduling With Active <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math> </inline-formula> Power Grids

Moudallal

Najm

2019

IEEE Trans. VLSI Syst.

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“…Spectral methods are playing increasingly important roles in many graph and numerical applications [30], such as scientific computing [28], numerical optimization [5], data mining [22], graph analytics [16], machine learning [9], graph signal processing [24], and VLSI computer-aided design [11], [35]. For example, classical spectral graph partitioning (data clustering) algorithms embed original graphs into low-dimensional space using the first few nontrivial eigenvectors of graph Laplacians and subsequently perform graph partitioning (data clustering) on the low-dimensional graphs to obtain high-quality solution [22].…”

Section: Introductionmentioning

confidence: 99%

“…immediately leads to a series of theoretically nearly-lineartime numerical and graph algorithms for solving sparse matrices, graph-based semi-supervised learning (SSL), spectral graph partitioning (data clustering), and max-flow problems [5], [17], [27], [28]. For example, sparsified circuit networks allow for developing more scalable computer-aided (CAD) design algorithms for designing large VLSI systems [11], [35]; sparsified social (data) networks enable to more efficiently understand and analyze large social (data) networks [30]; sparsified matrices can be immediately leveraged to accelerate the solution computation of large linear system of equations [37]. To this end, a spectral sparsification algorithm leveraging an edge sampling scheme that sets sampling probabilities proportional to edge effective resistances (of the original graph) has been proposed in [25].…”

Section: Introductionmentioning

confidence: 99%

GRASS: Graph Spectral Sparsification Leveraging Scalable Spectral Perturbation Analysis

Feng

2020

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Spectral graph sparsification aims to find ultrasparse subgraphs whose Laplacian matrix can well approximate the original Laplacian eigenvalues and eigenvectors. In recent years, spectral sparsification techniques have been extensively studied for accelerating various numerical and graph-related applications. Prior nearly-linear-time spectral sparsification methods first extract low-stretch spanning tree from the original graph to form the backbone of the sparsifier, and then recover small portions of spectrally-critical off-tree edges to the spanning tree to significantly improve the approximation quality. However, it is not clear how many off-tree edges should be recovered for achieving a desired spectral similarity level within the sparsifier. Motivated by recent graph signal processing techniques, this paper proposes a similarity-aware spectral graph sparsification framework that leverages efficient spectral off-tree edge embedding and filtering schemes to construct spectral sparsifiers with guaranteed spectral similarity (relative condition number) level. An iterative graph densification scheme is also introduced to facilitate efficient and effective filtering of off-tree edges for highly ill-conditioned problems. The proposed method has been validated using various kinds of graphs obtained from public domain sparse matrix collections relevant to VLSI CAD, finite element analysis, as well as social and data networks frequently studied in many machine learning and data mining applications. For instance, a sparse SDD matrix with 40 million unknowns and 180 million nonzeros can be solved (1E-3 accuracy level) within two minutes using a single CPU core and about 6GB memory.

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“…Request permissions from Permissions@acm.org. processing [16], and VLSI computer-aided design [9,23]. For example, classical spectral graph partitioning (data clustering) algorithms embed original graphs into low-dimensional space using the first few nontrivial eigenvectors of graph Laplacians and subsequently perform graph partitioning (data clustering) on the low-dimensional graphs to obtain highquality solution [14].…”

Section: Introductionmentioning

confidence: 99%

Similarity-aware spectral sparsification by edge filtering

Feng

2018

Proceedings of the 55th Annual Design Automation Conference

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In recent years, spectral graph sparsification techniques that can compute ultra-sparse graph proxies have been extensively studied for accelerating various numerical and graphrelated applications. Prior nearly-linear-time spectral sparsification methods first extract low-stretch spanning tree from the original graph to form the backbone of the sparsifier, and then recover small portions of spectrally-critical off-tree edges to the spanning tree to significantly improve the approximation quality. However, it is not clear how many off-tree edges should be recovered for achieving a desired spectral similarity level within the sparsifier. Motivated by recent graph signal processing techniques, this paper proposes a similarity-aware spectral graph sparsification framework that leverages efficient spectral off-tree edge embedding and filtering schemes to construct spectral sparsifiers with guaranteed spectral similarity (relative condition number) level. An iterative graph densification scheme is introduced to facilitate efficient and effective filtering of offtree edges for highly ill-conditioned problems. The proposed method has been validated using various kinds of graphs obtained from public domain sparse matrix collections relevant to VLSI CAD, finite element analysis, as well as social and data networks frequently studied in many machine learning and data mining applications.

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A Spectral Graph Sparsification Approach to Scalable Vectorless Power Grid Integrity Verification

Cited by 16 publications

References 13 publications

Power Scheduling With Active <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math> </inline-formula> Power Grids

Power Scheduling With Active <inline-formula> <tex-math notation="LaTeX">$RC$ </tex-math> </inline-formula> Power Grids

GRASS: Graph Spectral Sparsification Leveraging Scalable Spectral Perturbation Analysis

Similarity-aware spectral sparsification by edge filtering

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