A spread-spectrum clock generator with FIR-embedded binary phase detection and 1-bit high-order ΔΣ modulation

Xu, Ni; Shen, Yiyu; Lv, Sitao; Rhee, Woogeun; Wang, Zhihua

doi:10.1109/asscc.2015.7387452

Cited by 9 publications

(5 citation statements)

References 9 publications

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“…Three key techniques are employed to mitigate the phase-folding problem which is caused by nonlinearity of the BBPD: 1) adopting a high-order DS modulator with a 1-bit quantizer; 2) utilizing a hybrid FIR filter; 3) a two-point modulation technique is employed to further enhance linearity at the turning point of the triangular modulation profile [4]. We also show that the two-point modulation technique can improve the BBPLL performance by significantly reducing the frequency deviation or the peak phase deviation at the input of the BBPD [10].…”

Section: Introductionmentioning

confidence: 92%

“…In this work, we present a BBPLL-based SSCG which does not require the linear TDC, the linear DTC, or any background calibration circuitry to achieve the linear modulation [10]. Three key techniques are employed to mitigate the phase-folding problem which is caused by nonlinearity of the BBPD: 1) adopting a high-order DS modulator with a 1-bit quantizer; 2) utilizing a hybrid FIR filter; 3) a two-point modulation technique is employed to further enhance linearity at the turning point of the triangular modulation profile [4].…”

Section: Introductionmentioning

confidence: 99%

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A Two-Point Modulation Spread-Spectrum Clock Generator With FIR-Embedded Binary Phase Detection and 1-Bit High-Order ΔΣ Modulation

Xu¹,

Shen²,

Lv³

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper describes a spread-spectrum clock generation method by utilizing a DS digital PLL (DPLL) which is solely based on binary phase detection and does not require a linear time-to-digital converter (TDC) or other linear digital-to-time converter (DTC) circuitry. A 1-bit high-order DS modulator and a hybrid finite-impulse response (FIR) filter are employed to mitigate the phase-folding problem caused by the nonlinearity of the bang-bang phase detector (BBPD). The DS DPLL employs a twopoint modulation technique to further enhance linearity at the turning point of a triangular modulation profile. We also show that the two-point modulation is useful for the BBPLL to improve the spread-spectrum performance by suppressing the frequency deviation at the input of the BBPD, thus reducing the peak phase deviation. Based on the proposed architecture, a 3.2 GHz spread-spectrum clock generator (SSCG) is implemented in 65 nm CMOS. Experimental results show that the proposed SSCG achieves peak power reductions of 18.5 dB and 11 dB with 10 kHz and 100 kHz resolution bandwidths respectively, consuming 6.34 mW from a 1 V supply.

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Section: Introductionmentioning

confidence: 92%

Section: Introductionmentioning

confidence: 99%

A Two-Point Modulation Spread-Spectrum Clock Generator With FIR-Embedded Binary Phase Detection and 1-Bit High-Order ΔΣ Modulation

Xu¹,

Shen²,

Lv³

et al. 2016

JSTS:Journal of Semiconductor Technology and Science

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“…The high-order MASH modulator, however, generates more spread bit pattern than a single-loop ∆Σ modulator (SLDSM), causing a large DJ effect at the BBPD input. When the dynamic range of the input frequency is much smaller than the reference frequency, it is shown that a high-order SLDSM with a 1-bit quantizer outperforms the high-order MASH [5]- [7]. Fig.…”

Section: A Single-bit Vs Multi-bit δς Modulationmentioning

confidence: 99%

“…Recently, several BB-DPLL architectures without relying on the high-resolution DTC are proposed for frequency modulation. The DTC-free BB-DPLL with a single-bit ∆Σ modulator is proposed, but the in-band noise is relatively high [5]. The use of a few-bit DTC can reduce the in-band noise to about -90dBc/Hz without background digital calibration [6]- [7], but the initial calibration of the DTC for different frequencies is still needed.…”

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confidence: 99%

Design and Analysis of DTC-Free ΔΣ Bang-Bang Phase-Locked Loops

Wan

Rhee

Wang

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper discusses different design aspects of the ∆Σ fractional-N bang-bang PLL (BBPLL) compared with conventional analog or digital fractional-N PLLs performing linear phase detection. Several in-band noise reduction methods without relying on a high-performance digital-to-time converter (DTC) are considered at the architecture-level. It is shown that two-stage topology, single-bit ∆Σ modulation, and phase-domain filtering methods can improve the in-band phase noise, which is different from the conventional PLLs. It is also shown that two-point modulation is superior to one-point modulation regardless of data rate when an overdamped BBPLL is employed for frequency modulation. By integrating those in-band noise reduction methods, we propose a DTC-free, calibration-free ∆Σ BBPLL architecture that achieves the inband noise of about -100dBc/Hz. Behavioral simulation results show that the in-band noise performance can be improved by nearly 40dB without having the DTC.

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“…SSC generators are implemented based on four methods. The first approach consists of a fractional-N frequency divider, generally using a delta-sigma modulator [1][2][3][4][5]. The main advantage of this method is its robustness.…”

Section: Introductionmentioning

confidence: 99%

Low‐jitter spread spectrum clock generator using charge pump frequency detector in 0.18 μm CMOS for USB3.1 transceivers

Sadrafshari

Eskandari

Hadidi

et al. 2017

IET Circuits, Devices & Systems

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This study presents a spread spectrum clock generator (SSCG) circuit for high-speed applications. The proposed SSCG adopts a phased locked loop with two dual voltage-controlled oscillators and a frequency modulation loop implemented with a novel control unit to achieve the desired spectrum-spreading profile. The control unit consists of an analogue charge pump-based frequency comparator that can determine the deviation of spread spectrum clock frequency from the reference frequency. Using this analogue frequency comparator simplifies the SSCG control unit and mitigates the design constraints, particularly the speed requirements of SSCG control unit. Hence, the structure becomes a suitable solution for high-speed applications. The proposed SSCG is tailored for USB3.1 standard with −4000 to −5000 ppm down spreading at 5 GHz clock frequency and 30-33 kHz modulation frequencies. The circuit is designed in TSMC 0.18 μm 1P6M CMOS process that occupies 0.13 mm 2 active area. Based on simulation results, with a 1.8 V supply, it consumes 53.46 mW. The RMS value of absolute jitter at 5 GHz output of non-spread spectrum is 1.1 ps rms, and the EMI reduction is 22.7 dB with −5000 ppm down spread. The simulation results of the proposed system are compared with recent works.

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A spread-spectrum clock generator with FIR-embedded binary phase detection and 1-bit high-order ΔΣ modulation

Cited by 9 publications

References 9 publications

A Two-Point Modulation Spread-Spectrum Clock Generator With FIR-Embedded Binary Phase Detection and 1-Bit High-Order ΔΣ Modulation

A Two-Point Modulation Spread-Spectrum Clock Generator With FIR-Embedded Binary Phase Detection and 1-Bit High-Order ΔΣ Modulation

Design and Analysis of DTC-Free ΔΣ Bang-Bang Phase-Locked Loops

Low‐jitter spread spectrum clock generator using charge pump frequency detector in 0.18 μm CMOS for USB3.1 transceivers

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